Half-duplex/simplex digital signal converter

Abstract

A solid state circuit, which serves as a twin simplex/half-duplex converter, includes a triple input NAND gate. The output of the NAND gate is connected directly to the outgoing simplex conductor. Signals on the incoming simplex conductor are applied to the three inputs of the NAND gate through separate signal paths which introduce different delays. One signal path introduces an intermediate delay before applying the incoming signal to the NAND gate in an inverted form. The half-duplex line is connected to this signal path. While incoming signals are applied to all three inputs to the NAND gate as well as to the half-duplex line, a lack of coincidence at the inputs prevents any incoming signal from passing through the converter to the outgoing simplex line.

Dependencies are inferred from the claim text.