Inverse two-dimensional transform processor
AssigneeGeneral Electric Company
InventorsPasquale A. Merola, Marshall K. Quick
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Abstract
A processor capable of performing a two-dimensional inverse transform on high speed analog data and outputing the results in a display compatible format. The processor utilizes two charge coupled devices (CCD's), two matrix multipliers, which each perform a one-dimensional transform. The one-dimensional transformed data is multiplexed into a series to parallel converter so that another matrix multiplier can complete the two-dimensional transformation of the analog data.
Claims4
An inverse two-dimensional transform processor sampling N samples of source data within an N.times.N sub-block of data received at a source decoder comprising:
- a plurality of matrix multiplier means accepting said source data, each of said matrix multiplier means calculating N one-dimensional transformed data samples, each of said matrix multiplier means having N input terminals and N output terminals;
- a plurality of N to 1 multiplexers, each having N input terminals and 1 output terminal, each of said multiplexers being connected to one of said matrix multiplier means so that each output terminal of one of said matrix multiplier means is connected to one of said N input terminals of one of said multiplexers;
- a switching means accepting sequential samples from each of said N to 1 multiplexers and ordering them so that they are in a serial order;
- a series to parallel data converter means accepting said serial samples in a serial order from said switching means and transforming the order of said samples into a parallel order;
- a second matrix multiplier means accepting N samples in a parallel order from said series to parallel data converter and yielding N one-dimensional transformed coefficients;
- and
- a second N to 1 multiplexer, each input terminal of said second N to 1 multiplexer being connected to one of N output terminals of said second matrix multiplier means in order to yield said transformed coefficients from said second matrix multiplier in a serial order.
An inverse two-dimensional transform processor sampling N samples of source data within an N.times.N sub-block of data received at a source decoder comprising:
- a first matrix multiplier means accepting said source data and calculating N one-dimensional transformed data samples, said first matrix multiplier means having N input terminals and N output terminals;
- a first N to 1 multiplexer, each input terminal of said multiplexer being connected to each of the N output terminals of said first matrix multiplier means;
- a series to parallel data converter means accepting samples in a serial order from said first N to 1 multiplexer and transforming the order of said samples into a parallel order;
- a second matrix multiplier means accepting N samples in a parallel order from said series to parallel data converter and yielding N transformed coefficients;
- and
- a second N to 1 multiplexer, each input terminal of said second N to 1 multiplexer being connected to one of the N output terminals of said second matrix multiplier means in order to yield said transformed coefficients from said second matrix multiplier in a serial order.
Dependencies are inferred from the claim text.