Noise immunity in input buffer circuit for semiconductor memory
AssigneeTexas Instruments Incorporated
InventorsEdmund A. Reese, Lionel S. White, Jr., Joseph C. McAlexander, III
Life of this patent
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Abstract
A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.
Claims6
An input buffer circuit of improved noise immunity for a semiconductor memory comprising:
- a bistable differential voltage detector having first and second field effect transistors, each having a source-to-drain path and a gate, the gates of the first and second transistors providing inputs to the detector,
- means for coupling an input terminal to the gate of said first transistor,
- means for coupling a reference voltage to the gate of said second transistor,
- a pair of output transistors each having a source-to drain path and a gate with the source-to-drain paths being separately connected in series between the source-to-drain paths of the first and second transistors and a clocked supply voltage,
- third and fourth field effect transistors each having a source-to-drain path and a gate, the source-to-drain paths of the third and fourth field effect transsistors being separately connected from the gates of said pair of output transistors to reference potential, and the gates of the third and fourth transistors being connected to logic voltages from the output transistors,
- means for improving noise immunity including means for increasing the threshold voltages of the third and fourth transistors to a level significantly higher than that of said pair of output transistors, wherein the threshold voltage of the first and second transistors is significantly less than that of an enhancement mode field effect transistor.
Dependencies are inferred from the claim text.