Data recovery system for use with a high speed serial link between two subsystems in a data processing system

In a data processing system having a plurality of subsystems and a bit serial transmission line for transmitting serial data between said plurality of subsystems, the improvement comprising:

• encoding means at each of said stations for encoding the serial data into phase encoded pulses for transmission over said bit serial transmission line, the phase encoded pulses having at least a first transition during each bit period of the phase encoded pulses and having a second transition during each bit period to represent one of two data values;
• and
• data recovery means at each of said stations for recovering the data from the phase encoded pulses, said data recovering means including:
• means for generating a control signal having a transition for indicating the presence or absence of the second transition during each bit period of the phase encoded pulse, said means for generating including means for delaying the phase encoded pulses by a period greater than the period during each bit period after which the second transition would have occurred, means for receiving the delayed phase encoded pulses and the control signal fed back from the output of said means for generating in order to generate a control clock signal, and means for sampling the phase encoded pulses in response to the control clock signal in order to provide the control signal;
• means for generating a clock signal recovered from the phase encoded pulses, including means for delaying the phase encoded pulses by one-half bit period and logic circuitry for receiving the control signal, the phase encoded pulses and the one-half bit period delayed signal, and providing in response thereto the recovered clock signal;
• and
• means for generating a data signal recovered from the phase encoded pulses, including cascaded two-state device means for receiving the control signal and being clocked by the recovered clock signal in order to provide the recovered data signal.

In a data processing system having a plurality of subsystems linked by a bit serial transmission line, a data recovery system for recovering a data signal and a clock signal from a phase encoded pulse signal transmitted over the bit serial transmission line, the improvement wherein said data recovery system comprises:

• means for generating a three-quarter bit period time delayed phase encoded pulse signal from the phase encoded pulse signal;
• means for receiving the three-quarter bit time delayed signal and generating a control clock signal having a transition at three-quarter bit period points of the phase encoded pulse signal;
• means for sampling the phase encoded pulse signal at three-quarter bit period points in response to the control clock signal;
• means for generating a one-half bit period time delayed phase encoded pulse signal from the phase encoded pulse signal;
• means for generating a recovered clock signal from the phase encoded pulse signal by logically combining the phase encoded pulse signal, the one-half bit period time delayed signal, and the control signal;
• and
• means for generating a recovered data signal from said phase encoded pulse signal, including cascaded flip-flop means receiving the control signal and clocked by the recovered clock signal and Exclusive OR gate means for logically combining the outputs of said cascaded flip-flop means in order to provide the recovered data signal.