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US 4,287,577 AGranted
Interleaved TDMA terrestrial interface buffer
AssigneeCommunications Satellite Corporation
InventorJoseph H. Deal, Jr.
Life of this patent
Estimating the term…
Abstract
A common memory is used for asynchronous interleaved read and write operations. TDMA data compression and expansion is performed without ping-pong memories and elastic buffering is also possible. A buffer reset method is used to automatically slip a fixed number of bits in response to excessive phase shift between the read and write clock.
Claims19
A buffer memory system comprising:
- a Random Access Memory (RAM) having a data input terminal for receiving input data to said RAM, a data output terminal for providing output data from said RAM, an address input terminal for receiving signals indicative of address locations within said RAM and a read/write input terminal for receiving read and write signals, said memory storing said input data at an input address location in response to a write signal and an input address signal and providing output data from an output address location in response to an output address signal and a read signal;
- input address means for providing an input address to said address input terminal in response to an enabling signal;
- output address means for providing an output address to said address input terminal in response to an enabling signal;
- enabling means for providing nonoverlapping enabling signals to said input and output address means to thereby multiplex said input and output address signals onto said address input terminal;
- and
- read/write means synchronized with said enabling means for providing non-overlapping read and write signals to said read/write terminal.
3 more elements
A buffer memory system for asychronously writing in and reading from the same memory, said system comprising:
- a random access memory (RAM) having a data input terminal for receiving input data, a data output terminal for providing output data, an address input terminal for receiving an address signal which defines an addressed memory location, and a read/write control terminal for receiving read and write signals, said memory storing said input data at an addressed memory location in response to a write signal and providing output data from an addressed memory location in response to a read signal;
- input address means having an enabling terminal for receiving an input enabling signal, said input address means providing an input address to said address input terminal in response to said input enabling signal;
- output address means having an enabling terminal for receiving an output enabling signal, said output address means providing an output address to said address terminal in response to said output enabling signal;
- enabling means for providing non-overlapping enabling signals to said input and output address means to thereby multiplex said input and output address signals onto said address input terminal;
- and
- read/write means synchronized with said enabling means for providing non-overlapping read and write signals to said read/write terminal.
3 more elements
Dependencies are inferred from the claim text.