Sense amplifying system for memories with small cells

A sense amplifying system comprising;

• first and second access lines,
• a differential amplifier,
• first and second isolation devices coupling said differential amplifier to said access lines,
• means for controlling said first and second isolation devices independently, and
• means for charging each of said first and second access lines to a voltage of a predetermined magnitude.

A sense amplifying system comprising;

• first and second bit lines,
• an amplifying latch,
• a first isolation device connected between said first bit line and one side of said amplifying latch,
• a second isolation device connected between said second bit line and the opposite side of said amplifying latch,
• first means for controlling said first isolation device,
• second means for controlling said second isolation device, and
• means for charging each of said first and second bit lines to a voltage of a predetermined magnitude.

A sense amplifying system comprising;

• first and second bit lines,
• first and second differential amplifiers,
• first and second isolation devices connected between said first differential amplifier and said first and second bit lines,
• third and fourth isolation devices connected between said second differential amplifier and said first and second bit lines,
• first means for controlling said first and fourth isolation devices,
• second means for controlling said second and third isolation devices, and
• means for charging said first and second bit lines.

A memory comprising;

• an array including;
• first, second, third and fourth consecutively and parallelly arranged bit lines, a plurality of parallel word lines arranged orthogonal to said bit lines and a cell disposed at the intersection of each of said bit and word lines,
• a first sense amplifying system;
• first and second tandemly arranged differential amplifiers connected to the ends of said first and third bit lines at one edge of said array,
• first means including a first pair of isolation devices for selectively coupling said first differential amplifier to said first and third bit lines,
• second means including a second pair of isolation devices for selectively coupling said second differential amplifier to said first and third bit lines, and
• third means for establishing a reference potential coupled to said first and third bit lines, and
• a second sense amplifying system including;
• third and fourth tandemly arranged differential amplifiers connected to the ends of said second and fourth bit lines at an edge of said array opposite to that of said one edge,
• fourth means including a third pair of isolation devices for selectively coupling said third differential amplifier to said second and fourth bit lines,
• fifth means including a fourth pair of isolation devices for selectively coupling said fourth differential amplifiers to said second and fourth bit lines, and
• sixth means for establishing said reference potential coupled to said second and fourth bit lines.