High speed high density, multi-port random access memory cell
AssigneeInternational Business Machines Corporation
InventorsDavid B. Eardley, Richard E. Matick
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorsDavid B. Eardley, Richard E. Matick
Estimating the term…
A random access memory system is disclosed in which data stored in two distinct memory locations defined by distinct address signals can be non-destructively read out simultaneously. The system employs a matrix of two-port memory cells, each cell functioning to store one binary bit of data in a conventional cross-coupled common emitter flip-flop. A pair of input/output transistors have their emitters connected to the respective control nodes of the static cell, their bases connected to first and second word lines, and their collectors connected to first and second bit sense lines. The word lines and bit lines are addressed and pulsed such that during reading of the selected cells, current flows through only one of the input transistors of one of the cells of a sense line whereon, during writing, current flows through both of the input/output transistors, the direction of current flow during writing depending on the value of the binary bit being stored. The input/output transistors associated with each cell are integrated onto the chip and occupy only slightly more area than multi-configured devices conventionally employed in prior art two-port cells.
In a random access memory system comprising a plurality of bit storage cells any two of which are individually addressable during a reading operation to simultaneously provide to first and second sense amplifiers, signals corresponding to the binary value of the data stored in said cells at said two addressed locations, said locations being defined by two separate address signals;
In a random access memory system comprising a plurality of memory cells each of which includes a bistable semiconductor circuit having first and second control nodes, the improvement comprising:
In a random access memory system comprising a matrix of memory cells each of which includes a bistable semiconductor circuit having first and second control nodes, the improvement comprising:
Dependencies are inferred from the claim text.