Semiconductor memory device
AssigneeFujitsu Limited
InventorToshitaka Fukushima
Life of this patent
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Abstract
In a semiconductor memory device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a fuse and a PNP type transistor. An N type epitaxial layer is used as a word line and the P type semiconductor substrate is used as a collector output line.
Claims10
A semiconductor memory device comprising:
- a plurality of bit lines;
- a plurality of word lines;
- a plurality of memory cells operatively connected to and located at a cross position of said plurality of bit lines and said plurality of word lines, wherein each of said memory cells comprises an information storing element having a first terminal and a PNP type transistor connected in series with said information storing element, wherein said PNP type transistor comprises a P type semiconductor substrate, having a surface, forming the collector region;
- an N type epitaxial layer, formed on the surface of said P type semiconductor substrate, forming the base region;
- and a P type region, formed in said N type epitaxial layer, forming the emitter region, wherein said first terminal of said information storing element is operatively connected to one of said plurality of bit lines, wherein the base region of said PNP type transistor is operatively connected to one of said plurality of word lines, and wherein the collectors of the PNP type transistor of each of said plurality of memory cells are operatively connected at a node.
A semiconductor memory device having a plurality of PNP type transistors comprising:
- a P type semiconductor substrate having a surface;
- an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate;
- a P type region formed on the surface of said N type epitaxial layer;
- an N.sup.+ type region formed in said P type region;
- and
- a connecting conductor layer connected to said N.sup.+ type region, wherein said connecting conductor layer is a bit line, wherein said N type epitaxial layer is a word line, and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
A semiconductor memory device comprising:
- a P type semiconductor substrate having a surface;
- an N type epitaxial layer, having a surface, formed on the surface of said P type semiconductor substrate;
- a P type region formed on the surface of said N type epitaxial layer;
- and
- a connecting conductor, forming a bit line;
- a fuse connected between said P type region and said connecting conductor, wherein said N type epitaxial layer is a word line and wherein said P type semiconductor substrate is a collector which is commmon to the plurality of PNP type transistors.
A semiconductor memory device having memory cells, comprising:
- a P type semiconductor substrate having a surface;
- an N type epitaxial layer former on the surface of said P type semiconductor substrate;
- a P type epitaxial layer, having a surface, formed on the surface of said N type epitaxial layer;
- a first isolation region, formed from the surface of said P type epitaxial layer to a predetermined depth in the N type epitaxial layer, for isolating the memory cells;
- and
- a second isolation region, formed from the surface of said P type epitaxial layer through said N type epitaxial layer to a predetermined depth in said P type semiconductor substrate, for defining a word line formed by said N type epitaxial layer.
Dependencies are inferred from the claim text.