US 4,287,566 A · Array processor with parallel operations per instruction

Abstract

An array processor particularly useful in performing calculations utilizing data from two distinct two-dimensional arrays. More particularly, the array processor provided by the invention incorporates multiplication, addition, subtraction, transfer and storage means whereby arithmetic and storage operations, and two-dimensional array access operations can be conducted in parallel, thereby reducing the time required for complex and cumulative vector computations which could be associated with voice digital encoding and decoding systems. An architecture scheme is described which allows parallel operations to be effected, and a simplified addressing means is disclosed for vectorally accessing locations within two two-dimensional arrays. In addition, a coding and instruction scheme is disclosed which is compatible with the disclosed architecture.

Claims11

Dependent claims

An array processor comprising:

multiplication means;
multiplication input means to said multiplication means, said multiplication input means comprising first and second input registers;
first and second latch means each of which is operatively connected to at least one of said input registers;
output means from said multiplication means;
storage means;
addition and subtraction means responsive to contents of said multiplication output means and said storage means;
first and second arrays;
means for providing signal inputs from said first and second arrays to said multiplication input means, said storage means, and said addition and subtraction means;
and
interconnection means allowing selected multiplication, storage, addition and subtraction, and transfer operations to occur in parallel in response to predetermined input instructions, said interconnection means comprising means for connecting said first latch means to said first array and said second latch means to said second array.

7 more elements

An array processing system comprising:

a first two-dimensional array;
means for accessing said first array;
a second two-dimensional array;
means for accessing said second array;
a multiplication means;
first and second multiplication means input registers;
first and second multiplication means output registers;
first and second latch registers;
first, second, and third adders;
first, second, third and fourth storage registers;
a first bus;
a second bus;
interconnection means for connecting said first bus to said first array, said first latch, said first and second input registers, said second and third adders, and said first storage register;
interconnection means for connecting said second bus to said second array, said second latch, said first and second input registers, said second and third adders, and said fourth storage register;
interconnection means for connecting said first latch to said first input registers;
interconnection means for connecting said second latch to said second input register;
interconnection means for connecting said first multiplication means output register to said first, second, and third adders;
interconnection means for connecting said second multiplication means output register to said second and third adders;
interconnection means for connecting said first adder output to said first and second storage registers;
interconnection means for connecting said second adder output to said second and third storage registers;
interconnection means for connecting said third adder output to said third and fourth storage registers;
interconnection means for connecting said first storage register output to said first bus and said first and second adders;
interconnection means for connecting said second storage register output to said first bus, said second bus, said second adder and said third adder;
interconnection means for connecting said third storage register to said first bus, said second bus, said second adder and said third adder;
interconnection means for connecting said fourth storage register to said second bus and said third adder;
and
control means whereby a single input instruction can cause multiplication, addition, subtraction, and transfer operations within said system to occur simultaneously.

24 more elements

Dependencies are inferred from the claim text.

Array processor with parallel operations per instruction

Life of this patent

Array processor with parallel operations per instruction

Life of this patent

Abstract

Claims11