Real time adapter unit for use in a data processing system

A data processing system including a central processing unit and a controller coupled to a common bus, said controller having a number of ports for connecting a corresponding number of adapter units and including means for generating read commands to said adapter units, one of said adapter units comprising:

• a microprocessing section coupled to receive commands from said controller, said section including:
• a data bus;
• an address bus;
• microprocessing means coupled to said data and address buses;
• random access memory means having a plurality of storage locations, a number of said plurality of storage locations providing a multibyte transfer buffer, said random access memory means being coupled to said data bus and to said address bus;
• read only memory means having a plurality of storage locations for storing a number of instruction control sequences, said read only memory means being coupled to said address and data buses;
• peripheral interface adapter circuit means for transferring data, said peripheral interface adapter circuit means being coupled to said address bus and to said data bus and to a bidirectional peripheral data bus;
• a time of day counter section being coupled to said microprocessing section, said time of day counter section including:
• counter means for storing a predetermined number of bytes corresponding to a time of day value, said free running counter means being coupled to said peripheral interface circuit means and to said data bus;
• free running clock circuit means coupled to said counter means for generating clock signals for updating said time of day value at a predetermined rate;
• output latch register circuit means coupled to said counter means and to said data bus;
• and,
• decoder circuit means coupled to said bidirectional peripheral data bus and to said output register circuit means;
• and,
• selector circuit means coupled to said address bus, to said output latch register means and to said peripheral interface adapter circuit means, said microprocessing means being operative in response to a read command from said controller to read out instructions of a predetermined one of said instruction control sequences from said read only memory means for generating address and data signals on said address bus and data bus respectively, said selector circuit means being operative in response to said address signals to enable said peripheral interface adapter circuit means to apply said data signals on said peripheral bus to said decoder circuit means, said decoder circuit means in response to said data signals generating a series of output pulse signals for storing successive time of day values read from said counter means in said output latch register means, and said selector circuit means being operative in response to other address signals generated by said microprocessing means to enable said output latch register circuit means to transfer a predetermined byte of each successive time of day value to said microprocessing means for comparison to select the latest time of day value read from said counter means not during an update operation for loading into said transfer buffer of said random access memory means for transfer to said central processing unit in response to one of said read command applied to said one of said adapter units.

A data processing system including a central processing unit and a controller coupled in common to a bus, said controller having a number of ports for connecting a corresponding number of adapter units and including means for generating commands to said adapter units, one of said adapter units comprising:

• a microprocessing section coupled to said controller for transferring and receiving signals from said controller, said section including:
• a data bus;
• an address bus;
• a microprocessing unit coupled to said data bus and to said address bus;
• random access memory having a plurality of storage locations, a number of said plurality of storage locations providing a transfer buffer, said random access memory being coupled to said data and address buses;
• a programmable read only memory coupled to said address and data buses having a plurality of storage locations for storing a number of instruction control sequences;
• a clock circuit coupled to said controller for receiving timing signals from said controller and being coupled to said microprocessing section, said clock circuit for generating timing signals for synchronizing at a microsecond rate the operations of said microprocessing section within said adapter;
• a peripheral interface adapter circuit coupled to said data bus and to first and second bidirectional peripheral data buses, said peripheral interface adapter circuit including a pair of control registers, each coupled to said data bus and a different one of said first and second peripheral buses, each of said registers storing control information for separately controlling the direction of data for each line of the corresponding one of said peripheral data buses;
• a time of day counter section coupled to said microprocessing section, said time of day counter section including:
• a binary counter coupled to said first peripheral bus, said counter for storing a time of day value;
• a free running clock circuit coupled to said binary counter for generating clock signals for updating said time of day value at a millisecond rate;
• an output latching register coupled to said counter and to said data bus;
• and,
• a decoder circuit coupled to said second peripheral bus and to said output latch register;
• and,
• a selector circuit coupled to said address bus, to said output latch register and to an enable input terminal of said peripheral interface adapter circuit;
• said microprocessing unit being operative in response to a command from said controller requesting the time of day to read out a predetermined one of said instruction sequences from said read only memory for generating a succession of address and data signals on said address bus and data bus respectively, said selector circuit being operative in response to said address signals to apply a signal on said enable input terminal of said peripheral interface adapter circuit for applying said data signals on said second peripheral bus to said decoder circuit, said decoder circuit in response to said data signals generating a series of output pulses for storing a predetermined number of time of day values read from said counter in said output latching register and said selector circuit being operative in response to other address signals generated by said microprocessing unit to generate a series of output pulse signals to condition said output latch register to transfer a predetermined byte of each predetermined number of said time of day values to said microprocessing unit for comparison to select the latest time of day value read from said binary counter not during an update operation for storage in said transfer buffer of said memory for subsequent transfer to said central processing unit in response to said read command.