Dual mode microprocessor system

A universal-type microprocessor system which cooperates with an application-dependent logic module to form a peripheral-controller capable of handling data transfers between main memory of a host computer and a plurality of peripheral terminal units which can be either "word-oriented" or "byte-oriented", and wherein said application-dependent logic module provides external register means having bus connections to said plurality of peripheral terminal units and to said host computer, and wherein said application-dependent logic module further includes an external memory for storage of programs related to control of said peripheral terminal units and for temporary storage of data undergoing transfer, and wherein said application-dependent logic module further includes control logic means for communicating with and controlling said external register means, said external memory and communicating with a decoder-controller in said microprocessor system, the said microprocessor system comprising:

• (a) data processing means including:
• (a1) an Arithmetic Logic Unit providing an output to a shift logic circuit and to a byte-swap circuit;
• (a2) said shift logic circuit providing output to an I/O bus, said shift logic circuit functioning to rotate one or more bits of a word being processed, to the right or to the left;
• (a3) said byte-swap circuit providing output to said I/O bus, said byte-swap circuit functioning to exchange the sequential positions of the higher order byte and the lower order byte of a received two-byte word;
• (b) said I/O bus providing connecting lines from said data processing means to said external registers, to said external memory, to an accumulator register means, and to an addressing means;
• (c) said addressing means receiving input data from said I/O bus and storing addresses useful for accessing data from an internal memory or said external memory, said addressing means including:
• (c1) a program counter storing consecutive addresses of data located in said internal program memory;
• (c2) a memory reference register for storing addresses of data located in said external memory, and including:
• (c2-1) a memory address bus which connects to said external memory;
• (c2-2) and wherein a dedicated non-address bit in each location in said memory reference being set to signal said decoder-controller to initiate a byte-swap operation in said byte-swap circuit, or when not-set, to pass data without a byte-swap operation;
• (c2-3) a bus connection from said memory reference register to said decoder-controller;
• (c3) an address register in said decoder-controller connecting by means of an address bus to accumulator register means which include a plurality of accumulator registers for selection of data from/to an one of said addressed accumulator registers;
• (d) said internal program memory for storing program instructions and data words, said internal memory being addressed from said program counter and providing instruction words and data, via an instruction bus, to an instruction register and memory operand register, said program memory including:
• (d1) instruction words wherein each word includes a field (M) which signals said decoder-controller to select either said program counter or memory reference register as source of the next address;
• (e) register means for temporary storage of data, said register means including:
• (e1) said plurality of addressable accumulator registers which provide an output to the input of said Arithmetic Logic Unit, said accumulator registers receiving input data words from said I/O bus;
• (e2) said memory operand register for receiving operand data from said internal program memory via an instruction bus or from said external memory via a memory data bus;
• (e3) said instruction register for receiving instruction words from said internal program memory via said instruction bus or from said external memory via said memory data bus, and providing instruction words to said decoder-controller;
• (f) said instruction decoder-controller receiving instruction signals from said instruction register, and including incoming and outgoing control signal lines connected to said data processing means, to said addressing means, to said register means, to said internal and external memory means, to said external registers and said control logic means, said decoder-controller further including:
• (f1) means for setting operations into one of two modes wherein a first mode, designated foreground mode, is for normal operations and a second mode, designated background mode, is for interrupt operations;
• (g) an external memory data bus for carrying data from said external memory to said instruction register and said memory operand register;
• (h) and wherein said plurality of addressable accumulator registers includes:
• (h1) a first set of accumulator registers, designated as foreground accumulator registers, for use during normal operations;
• and
• (h2) a second set of accumulator registers, designated as background accumulator registers, for use during interrupt operations;
• (i) and wherein said decoder-controller includes:
• means to select an accumulator register in said first set or said second set according to whether the foreground mode or background mode is operating.