US 4,287,559 A · Electronic microprocessor system having two cycle branch logic

Abstract

An integrated chip microprocessor system has a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on such data, an instruction memory for storing a plurality of instruction words, a program counter for addressing the instruction memory, and an instruction word decoder for decoding instruction words outputted from the instruction memory for controlling the operation of the microprocessor system. The instruction word decoder has a branch decoder system for implementing a two cycle branch logic. Each program branch operation, as stored in the instruction memory has two parts: a branch instruction word which indicates a program branch and also indicates the state of a selected one of a plurality of flag latches upon which it is conditioned; and a branch address instruction word solely indicative of the instruction memory address to which the program is to branch, the branch address instruction word being stored in the next memory location in the instruction memory following the branch instruction word. The branch decoder system determines when a branch instruction word is outputted from the instruction memory and also determines if the program branch is conditional or unconditional, and if the branch is conditional, the particular state of a selected flag latch upon which the branch is conditioned. If the branch is unconditioned, or if the branch is conditional and the condition satisfied, the branch decoder system inserts the branch address instruction word which is the next instruction word outputted from the instruction memory into the program counter.

Claims8

Dependent claims

An electronic data processing system comprising:

(a) an instruction memory for storing a plurality of instruction words in sequential memory locations, said plurality of instruction words having at least one set of a branch instruction word followed by a branch address instruction word in the next sequential memory location, said branch address instruction word being solely indicative of one of said memory locations, said instruction memory further for outputting a particular instruction word upon reception of a memory address indicative of said memory location of said particular instruction word;
(b) a program counter for storing therein a memory address solely indicative of a particular memory location of said instruction memory including means for applying said memory address to said instruction memory;
(c) an instruction decoder logic means, responsive to instruction words outputted from said instruction memory, for decoding said instruction words, said decoder logic means including a branch instruction detection means for detecting when one of said instruction words is a branch instruction word;
and
(d) a branch logic system for setting said program counter to the address indicated by the instruction word stored in the sequential memory location immediately following the memory location wherein said detected branch instruction word is stored in response to the detection of said branch instruction word by said branch instruction detection means.

2 more elements

A method of performing branch operations in an electronic data processing system comprising the steps of:

(a) storing instruction words in sequential memory locations of an instruction memory including storing at least one branch instruction word and storing a correlated branch address instruction word, solely indicative of one of the memory locations, in the next sequential memory location following the memory location of said at least one branch instruction word;
(b) reading instruction words out of the instruction memory from a memory location indicated by the contents of a program counter;
(c) periodically changing the contents of the program counter to indicate the next sequential memory location in the instruction memory;
(d) determining whether a said instruction word read out of the instruction memory is a branch instruction word;
and
(e) changing the program counter to the indication of the memory location as found in the correlated branch address instruction word when it is determined that the instruction word read out of the instruction memory is determined to be a said branch instruction word.

3 more elements

A microprocessor branch system comprising:

(a) an instruction memory for storing a plurality of instruction words in sequential memory locations, including at least one set of a branch instruction word followed by a branch address instruction word, solely indicative of one of said sequential memory locations, in the next sequential memory location, said instruction memory further including means for outputting a particular instruction word upon reception of a memory address indicative of said memory location of said particular instruction word;
(b) an address register means for storing therein a said memory address indicative of a particular memory location of said instruction memory, for applying said memory address to said instruction memory, and for periodically altering said memory address stored therein to the memory address indicative of the next sequential memory location in said instruction memory;
(c) branch instruction detecting means responsive to instruction words outputted from said instruction memory for detecting when a branch instruction word is outputted;
and
(d) means responsive to said branch instruction detecting means for replacing the memory address stored in said address register means with said indication of one of said sequential memory locations as found in the next instruction word outputted from said instruction memory after said detection of said branch instruction word.

2 more elements

Dependencies are inferred from the claim text.

Electronic microprocessor system having two cycle branch logic

Life of this patent

Electronic microprocessor system having two cycle branch logic

Life of this patent

Abstract

Claims8