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US 4,287,526 AGranted
Insulated gate field effect transistor
AssigneeNippon Electric Co., Ltd.
InventorHiraku Sakuma
Life of this patent
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Abstract
An insulated gate field effect transistor is disclosed. The transistor comprises an insulator body, a semi-conductor layer of one conductivity type formed on a surface of the insulator body, a pair of source and drain regions of the opposite conductivity type formed in the semi-conductor layer along its one major surface and an extension region of the opposite conductivity type extending from one of the source and drain regions towards the remaining of the source and drain regions. A first insulating film is formed on the entire surface of the extension region, a gate insulating film is formed on a channel region of the transistor and a gate electrode is formed on the gate insulating film.
Claims17
An insulated gate field effect transistor, comprising:
- an insulator body having a generally planar major surface;
- a semiconductor layer of a first conductivity type formed on said insulator body major surface, said semiconductor layer having a generally planar, major surface lying parallel to said insulator body major surface;
- a source region of a second conductivity type, opposite of that of said first conductivity type, formed in said semiconductor layer along said major surface of said semiconductor layer;
- a drain region of said second conductivity type formed in said semiconductor layer along said major surface of said semiconductor layer and spaced from said source region with a channel region lying therebetween;
- an extension region of said second conductivity type formed in said semiconductor layer and extending from one of said source and drain regions to said channel region, said extension region having an impurity concentration lower than that of said one of said source and drain regions, one surface of said extension region being coincident with said major surface of said semiconductor layer, a second surface of said extension region being generally parallel to said insulator body surface and spaced therefrom such that a portion of said semiconductor layer lies between said second surface and said insulator body major surface, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion lying between said extension region and said insulator body;
- a first insulating film formed on the entire first surface of said extension region;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said gate film.
6 more elements
An integrated circuit device comprising an insulating member having a generally planar major surface and a plurality of insulated gate field effect transistors formed thereon, each of said transistors being isolated from the remaining said transistors and comprising:
- a semiconductor layer of a first conductivity type formed on said insulator body major surface, said semiconductor layer having a generally planar, major surface lying parallel to said insulator body major surface;
- a source region of a second conductivity type, opposite of that of said first conductivity type, formed in said semiconductor layer along said major surface of said semiconductor layer;
- a drain region of said second conductivity type formed in said semiconductor layer along said major surface of said semiconductor layer and spaced from said source region with a channel region lying therebetween;
- an extension region of said second conductivity type formed in said semiconductor layer and extending from one of said source and drain regions to said channel region, said extension region having an impurity concentration lower than that of said one of said source and drain regions, one surface of said extension region being coincident with said major surface of said semiconductor layer, a second surface of said extension region being generally parallel to said insulator body surface and spaced therefrom such that a portion of said semiconductor layer lies between said second surface and said insulator body major surface, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion lying between said extension region and said insulator body;
- a first insulating film formed on the entire first surface of said extension region;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said gate film.
5 more elements
An insulated gate field effect transistor, comprising:
- an insulator body;
- a semiconductor layer of one conductivity type on a surface of said insulator body;
- a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body;
- an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body;
- a channel region positioned between said extension region and the other of said source and drain regions;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said gate insulating film and not extending over said extension region.
5 more elements
An insulated gate field effect transistor, comprising:
- an insulator body;
- a semiconductor layer of a first conductivity type on a surface of said insulator body;
- a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer;
- an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions;
- an insulating gate film formed on the entire surface of said first surface;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.
5 more elements
An insulated gate field effect transistor, comprising:
- an insulator body;
- a semiconductor layer of one conductivity type on a surface of said insulator body;
- a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body;
- an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body, the total amount of effective impurity of said opposite conductivity type contained in said extension region being less than 120 percent and more than 80 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer located between said extension region and said insulator body;
- a channel region positioned between said extension region and the other of said source and drain regions;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said gate insulating film and not extending over said extension region.
5 more elements
An insulated gate field effect transistor, comprising:
- an insulator body;
- a semiconductor layer of a first conductivity type on a surface of said insulator body;
- a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer;
- an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer lying between said extension region and said insulator body;
- an insulating gate film formed on the entire surface of said first surface;
- a gate insulating film formed on said channel region;
- and
- a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.
5 more elements
Dependencies are inferred from the claim text.