Edge sense latch

An MOS edge sense latch comprising:

• a first MOS component responsive to an input signal having first and second states;
• a second MOS component coupled to said first MOS component and responsive to a clock signal having first and second states, said second MOS component including capacitance means which is charged when said input signal and said clock signal are at their respective first and second states and a gate means, said gate means being conductive when said input signal and said clock signal are at said respective second and first states or when said capacitance means contains a predetermined level of charge;
• and
• a latch circuit having an output terminal normally set to a first state and including third and fourth MOS components each having an input and an output, the input of said third MOS component being coupled to said gate means and to the output of said fourth MOS component, and the input of said fourth MOS component being coupled to said output terminal and to the output of said third MOS component, said output terminal being set to a second state only when said capacitance means contains said predetermined level of charge and said input signal changes to said second state.