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US 4,287,441 AGranted
Correlated double sampling CCD video preprocessor-amplifier
AssigneeThe United States of America as represented by the Secretary of the Army
InventorEdwyn D. Smith
Life of this patent
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Abstract
The invention provides a preprocessor using sample-and-hold circuits and lifiers which performs double correlated sampling of the output of a CCD with full efficiency at rates up to those at which these elements can perform individually.
Claims6
In combination with a charged couple device (CCD) having a periodic gated output a low level signal preprocessor comprising:
- a source of clock pulses having a preselected sampling frequency;
- a pair of sample-and-hold (S&H) circuits, each having a signal input, a clock input, an output and substantially equal signal gain characteristics, with their clock inputs coupled to and synchronized with said source and having their signal inputs each coupled to the output of the CCD;
- a delay line means having a specific insertion loss and coupled in series with a first of said S&H circuits to delay the signal therein by a fraction of a cycle of said sampling frequency;
- an attenuator means coupled in series with the second of said S&H circuits to attenuate the signal in said second S&H circuit by an amount equal to the insertion loss of said delay line means;
- and
- a single output circuit coupled to the outputs of both of said S&H circuits.
3 more elements
Dependencies are inferred from the claim text.