Gated oscillator
AssigneeRCA Corporation
InventorsNicholas Kucharewski, James E. Gillberg
Life of this patent
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Abstract
A gated oscillator implemented with cascade-connected inverting logic circuits and resistor-capacitor timing elements generates oscillations so long as an inhibiting signal is not applied to one of the logic circuits. Means are provided to maintain potentials on the timing elements during application of inhibiting signal, which potentials are equivalent to steady-state operating potentials at the inception of a state transition. When the inhibiting signal is discontinued allowing oscillations to be generated, the initial pulse period is equal to the steady-state pulse period.
Claims23
In an oscillator circuit of the type including a plurality of inverting circuits in cascade connection, at least one of which is a two-input LOGIC circuit susceptible of inhibiting oscillation responsive to a prescribed control signal being applied to one of its input connections, including a closed feedback path effected by a capacitor having first and second plates respectively connected between the respective input and output connections of the first and last of the inverting circuits in said cascade connection, and including a resistor connected between the first plate of the capacitor and the output connection of one of the inverting circuits in said cascade connection which is normally in a state complementary to said last inverting circuit, said oscillator alternating between two states responsive to potential at the interconnection of the capacitor and resistor traversing a threshold voltage V.sub.T, an improvement for producing an initial oscillatory period after cessation of applied control signal, which initial oscillatory period is of equal duration to the steady state oscillating period, which improvement comprises:
- means for generating and applying a potential substantially equal to V.sub.T to the interconnection of the capacitor and resistor whenever oscillation is inhibited, thereby conditioning the oscillator to operate within steady-state potential limits for the initial period;
- and
- means for conditioning each of the inverting circuits in said cascade connection to obtain a prescribed state, whenever oscillation is inhibited, to ensure the oscillator will change states immediately after cessation of applied control signal.
A selectively enabled, or gated, oscillator comprising:
- a first LOGIC circuit having input and output connections;
- and first and second terminals for applying supply potential therebetween, characterized by changing its state for an input signal excursion through a potential V.sub.T ;
- a second LOGIC circuit having a first input connected for receiving control signal, a second input connected to the output connection of the first LOGIC circuit and characterized by exhibiting an output signal complementary to the control signal for the control signal being in a first logic state, and exhibiting the complement of signal at its second input connection for the control signal being in a second logic state;
- a capacitor having a first plate connected to the output connection of the second LOGIC circuit and having a second plate;
- a resistor having a first end connected to the output connection of the first LOGIC circuit and a second end connected to the second plate of the capacitor;
- means connecting the second plate of the capacitor to the input connection of the first LOGIC circuit;
- means for selectively generating a threshold potential V.sub.T, which potential is applied to an interconnection between the resistor and capacitor;
- and
- switch means for selectively applying supply potential between the first and second terminals of the first LOGIC circuit for the oscillator enabled, and open otherwise, said switch means being arranged so that the output potential of the first LOGIC circuit tends toward the logic state that conditions the second LOGIC circuit to change state immediately subsequent to the control signal obtaining its second logic state.
A selectively disabled or gated oscillator comprising:
- first and second LOGIC circuits having respective first input connections for receiving a control signal, having respective output and second input connections for each characterized by exhibiting an output signal complementary to the control signal for the control signal being in a first logic state, and exhibiting the complement of the signal at its second input for the control signal being in a second logic state;
- a capacitor having a first plate connected at the output connection of the second LOGIC circuit and having a second plate;
- means connecting the second plate of the capacitor to the second input connection of the first logic circuit;
- a resistor connected between the second plate of the capacitor and the output of the first LOGIC circuit;
- means connecting the output connection of the first LOGIC circuit to the input connection of the second LOGIC circuit;
- means for generating a potential V.sub.T, equivalent to the steady-state d.c. potential appearing at the interconnection of the resistor and capacitor;
- and
- means for applying the potential V.sub.T to the interconnection of the resistor and capacitor.
A selectively disabled or gated oscillator comprising:
- first and second LOGIC circuits each having a first input connection for receiving a control signal each having an output and a second input connection and characterized by exhibiting an output signal state complementary to the control signal for the control signal in a first logic state and exhibiting an output signal complementary to the signal at its second input connection for the control signal in a second logic state;
- means for connecting the output connections of the first LOGIC circuit to the input connection of the second LOGIC circuit;
- a capacitor having a first plate connected to the output connection of the second LOGIC circuit and having a second plate;
- means connecting the second plate of the capacitor to the input connection of the first LOGIC circuit;
- an INVERTER circuit having first and second nodes for application of respective relatively positive and relatively negative supply potentials thereto, having an input connected to the output connection of the second LOGIC circuit and having an output connection;
- switch means between at least one of the first and second nodes and its associative supply potential for interrupting application of supply potential responsive to said control signal whenever the oscillator is disabled;
- a resistor having a first end connected to the output connection of the INVERTER circuit and a second end connected to the second plate of the capacitor, the resistor and capacitor establishing the frequency oscillation;
- means for generating a potential V.sub.T, substantially equal to the steady state d.c. potential occurring at the interconnection of the resistor and capacitor for the oscillator enabled;
- and
- means for applying the potential V.sub.T to the interconnection of one of the first and second nodes and the switch means.
In an oscillator circuit of the type including a plurality of inverting circuits in cascade connection, at least one of which is a two-input LOGIC circuit susceptible of inhibiting oscillation responsive to a prescribed control signal being applied to one of its input connections, including a closed feedback path effected by a capacitor having first and second plates respectively connected between the respective input and output connections of the first and last of the inverting circuits in said cascade connection, and including a resistor connected between the first plate of the capacitor and the output connection of one of the inverting circuits in said cascade connection which is normally in a state complementary to said last inverting circuit, said oscillator alternating between two states responsive to potential at the interconnection of the capacitor and resistor traversing a threshold voltage V.sub.T, an improvement for producing an initial oscillatory period after cessation of applied control signal, which initial oscillatory period is of equal duration to the steady state oscillating period, which improvement comprises:
- means responsive to said prescribed control signal for establishing a potential substantially equal to V.sub.T at the interconnection of the capacitor and resistor whenever oscillation is inhibited, thereby conditioning the oscillator to operate within steady-state potential limits for the initial period;
- and
- means for conditioning each of the inverting circuits in said cascade connection to obtain a prescribed state, whenever oscillation is inhibited, to ensure the oscillator will change states immediately after cessation of applied control signal.
Dependencies are inferred from the claim text.