Sense amplifier with dual parallel driver transistors in MOS random access memory
AssigneeTexas Instruments Incorporated
InventorsG. R. Mohan Rao, Lionel S. White, Jr.
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Abstract
A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with a bistable sense amplifier circuit at the center of each column. Instead of a single pair of cross-coupled driver transistors forming the bistable circuit, dual parallel pairs are used. One pair used in the initial sensing has a long channel length so that the pair may be more readily matched, while the other pair used later in the cycle for driving the zero-going side of the column line to ground has a shorter channel to enhance speed.
Claims11
A memory system of the type having an array of rows and columns of memory cells and a plurality of sense amplifiers, the sense amplifiers having inputs connected to each column, each sense amplifier comprising first and second pairs of cross-coupled driver transistors with each of such transistors having a source-to-drain path and a gate, each of the first pair of driver transistors having one end of its source-to-drain path directly cross connected to the gates of the other of said first and second pairs, each of the second pair of driver transistors having one end of its source-to-drain path directly cross connected to the gates of the other of said first and second pairs, the gates of the opposing transistors of the first and second pairs having the same voltages thereon throughout an operating cycle of the memory system, said one ends of the source-to-drain paths of both said first and second pairs being coupled together and to said columns whereby the source-to-drain paths of the first pair of driver transistors are in parallel with the source-to-drain paths of the second pair of driver transistors, means separately connecting the other ends of said source-to-drain paths of each of the first and second pairs of driver transistors to reference potential to render the first pair conductive prior to a selected time in an operating cycle and both the first and second pair conductive after said selected time in an operating cycle.
A sense amplifier for a semiconductor memory comprising first and second pairs of cross-coupled driver transistors and a pair of load transistors, each of said transistors having a current path and a control electrode, the current paths of the load transistors serially connecting the one end of the current paths of the pairs of driver transistors separately to a supply voltage, said one end of each of said current paths in each of the pairs of driver transistors being directly cross connected to the control electrode of the other driver transistor in the respective pair during all of an operating cycle, the other ends of each pair of driver transistors being separately connected to reference potential through one of a pair of coupling means to render the first pair conductive prior to a selected time in an operating cycle and both the first and second pair conductive after said selected time in an operating cycle.
Dependencies are inferred from the claim text.