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US 4,285,059 AGranted
Circuit for test of ultra high speed digital arithmetic units
AssigneeThe United States of America as represented by the Secretary of the Army
InventorsDonald W. Burlage, James F. Lancaster
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Abstract
A method is shown for testing ultra high speed digital arithmetic circuits r even complete digital signal processors which operate at speeds faster than presently available test equipment. With this technique for testing, the operating speed of digital circuits can be increased until failures occur and then quantitative information on failure rates can be measured.
Claims2
A method for testing ultra high speed digital equipment comprising the steps of selecting an input signal to be fed through the digital equipment;
- storing this input signal in a first shift register;
- selecting an expected output signal which should be presented if the input signal was fed through said digital equipment;
- storing this expected output signal in a second shift register;
- feeding the input signal from the first shift register into the digital equipment;
- and comparing the output from the digital equipment with the expected output signal stored in the second shift register to detect faults.
2 more elements
Dependencies are inferred from the claim text.