Information transfer control system

An information transfer control system for controlling bidirectional transfer of information comprising:

• first and second information processors;
• a first-in first-out memory provided between said first and second information processors for temporarily storing information transferred from said first or second information processor;
• bus means interconnecting said first information processor and said first-in first-out memory and interconnecting said second information processor and said first-in first-out memory whereby information can be transferred from said first and second processors to said first-in first-out memory and from said first-in first-out memory to said first and second information processors;
• status signal generating means in said first-in first-out memory for producing a FULL signal when said memory is substantially full of information and an EMPTY signal when said memory has no stored information;
• first direction signal generating means for producing a first direction signal specifying that information is to be transferred from said first information processor to said first-in first-out memory and for producing a second direction signal specifying that information is to be transferred from said memory to said first information processor;
• and
• first control means having input terminals connected to said status signal generating means and said first direction signal generating means and an output terminal connected to said first information processor and applying a first data transfer inhibit signal to said first information processor when said FULL signal and said first direction signal are present at the same time and when said EMPTY signal and said second direction signal are present at the same time.