US 4,285,037 AGranted

Circuit arrangement for a switching system

AssigneeSiemens Aktiengesellschaft

InventorHanns N. Von Stetten

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Abstract

A circuit arrangement for a switching system having microprocessors for decentralized execution of switch-oriented jobs is provided wherein a separate microprocessor, autonomously functional for its jobs, is provided in a network level for the connection of a respective class of connection lines with specific and identical transmission properties and in a switching level for the connection of devices respectively provided for executing specific and identical switching tasks and services. All microprocessors are connected with one another by way of a common data bus, whereby the transmission of messages in the transmitting and receiving directions between the microprocessors occurs in the form of information blocks provided with address information. A central clock pulse is provided, under whose control only one respective microprocessor is cyclically connectible for the transmission of an information block and all other microprocessors are connectible to the common data bus for the reception of an information block. Each microprocessor receives an information block only upon the presence of an address intended for the connection lines or devices connected to the microprocessor concerned.

Claims8

Dependent claims

A circuit arrangement for a switching system having microprocessors operable in a transmitting mode to transmit data and in a receiving mode to receive data and communicating with each other over a data bus carrying information blocks including addresses, for decentralized execution of switch-oriented functions, comprising:

a plurality of connection lines each having a respective address and each representing a data transmission speed and adapted for connection to data transmission/receiving devices;
a plurality of processing devices each of which has a respective address and is operable to perform a predetermined function;
a plurality of microprocessors each autonomously operable with respect to its own functions, first ones of said microprocessors being in a network level and each connected to at least one of said connection lines, and second ones of said microprocessors being in a switching level and connected to respective ones of said processing devices;
a data bus connected to each of said microprocessors for carrying the information blocks including addresses identifying said connection lines and said processing devices;
and
a clock pulse bus connected to each of said microprocessors for carrying cyclically occurring clock pulses for rendering a respective microprocessor connected to said data bus and operable in a transmitting mode to transmit an information block and all other microprocessors simultaneously connected to said data bus and operable in a receiving mode to receive an information block,
each of said microprocessors operable only in response to the address of the respective connection line or respective processing device connected thereto for receiving the information block containing the relevant address.

4 more elements

Dependencies are inferred from the claim text.