US 4,284,910 A · Address buffer for a MOS-memory module

Abstract

An address buffer is disclosed in MOS technology with an address memory circuit exhibiting an address input driven via a transfer signal and having two complementary address outputs and two complementary signal outputs of high signal level. An isolating amplifier is provided with a following-connected output stage. The isolating amplifier is driven via a control clock pulse and supplies complementary control signals. It also has two parallel paths each consisting of the driven segments of two transistors. These parallel paths are connected to the drive clock pulse at a first common node and are connected to a base voltage source at a second common node. The first transistor of each parallel path is driven via a respective high signal level signal output of the address memory circuit and the second transistor of each parallel path is driven via a respective address output of the address memory circuit which is inverse to the high level signal output.

Claims4

Dependent claims

An address buffer in MOS technology comprising:

an address memory circuit having an address input driven via a transfer signal, two complementary address outputs, and two complementary high signal level outputs;
an isolating amplifier;
a following-connected output stage;
the isolating amplifier being driven via a control clock pulse and having outputs for complementary control signals;
the isolating amplifier having two parallel paths each comprising two transistors, said parallel paths being connected to the control clock pulse via a first common node and being connected to a base voltage source via a second common node;
a first transistor of each parallel path being driven by a respective one of the two high signal level outputs of the address memory circuit;
and a second transistor of each parallel path being driven by a respective one of the two address outputs of the address memory circuit, the high signal level output driving the first transistor of one of the paths being the inverse of the address output driving the second transistor of the same path.

4 more elements

Dependencies are inferred from the claim text.

Address buffer for a MOS-memory module

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Address buffer for a MOS-memory module

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Abstract

Claims4