US 4,284,905 A · IGFET Bootstrap circuit

Abstract

An improved IGFET bootstrap driver circuit capable of driving a load impedance to substantially full VDD power supply voltage and holding the load at that voltage for an indefinite period of time. The circuit includes a load transistor, a feedback capacitor connected between the source and gate electrodes of the load transistor, a fix valued resistor connected between the gate electrode of the load transistor and an on-chip bias voltage generating circuit for providing a bias voltage greater than VDD+VT. The resistor and the bias voltage generating circuit provide sufficient current to replenish the charge lost from the feedback capacitor through junction leakage currents in the driver circuit. The resistor is of a sufficiently high value such that the current drain from the generating circuit is insignificantly small in comparison to the current drain from the VDD power supply. The improved circuit also permits the load transistor to be switched "on" or "off" by an externally applied signal.

Claims8

Dependent claims

An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, a second IGFET having its channel coupled between the first voltage supply terminal and the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal,

characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.

An IGFET driver circuit comprising a first voltage supply terminal adapted to carry a first bias voltage, an output node, a control node, a first IGFET having its channel coupled between the first voltage supply terminal and the output node, the gate of the first IGFET being coupled to the control node, capacitance means coupled between the output node and the control node, a second voltage supply terminal adapted to carry a second bias voltage, at least one input terminal for receiving an input signal, switching means coupled between the output node and the second voltage supply terminal, the switching means responsive to the input signal at the input terminal for providing a conducting path between the output node and the second voltage supply terminal.

characterized in that there are included a third voltage supply terminal adapted to carry a third bias voltage of greater magnitude than the first bias voltage, a clock input node for receiving a clock signal, a second IGFET having its channel coupled between the control node and the clock input node, the gate of the second IGFET being coupled to the first voltage supply terminal, and substantially fixed value resistance means coupled between the third voltage supply terminal and the control node.

Dependencies are inferred from the claim text.

IGFET Bootstrap circuit

Life of this patent

IGFET Bootstrap circuit

Life of this patent

Abstract

Claims8