Simplified electronic ignition timing and A/D conversion

Electronic spark timing angle apparatus for a spark ignition, internal combustion engine, comprising:

• means for providing cylinder signals indicative of the occurrence of each cylinder-related sub-cycle of the engine;
• means for providing engine angle signals delineating angular rotation of the engine within each cylinder-related sub-cycle of engine rotation, said engine angle signals indicating angles of rotation which are much smaller than the angles of rotation related to each cylinder-related sub-cycle of the engine;
• means operative in response to inlet manifold pressure of the engine for providing pressure signals indicative of engine loading;
• means for providing firing angle signals indicative of the desired spark firing angle as a function of engine speed and load in response to said pressure signals and a time function of said engine angle signals indicative of rotary speed of the engine;
• and
• counting means responsive to said firing angle signals, said cylinder signals, and said engine angle signals for counting a particular number of said engine angle signals which occur subsequent to each of said cylinder signals, said particular number in each case being determined by said firing angle signals, and for providing an end of dwell signal indicating the time of occurrence of the desired firing angle in response to completion of counting of said particular number of angle signals;
• characterized by said counting means including a pair of presettable counters, each having preset inputs, a preset enable input connected to said cylinder signals, a clock input connected to said angle signals, a clock enable input and an overflow output;
• and
• logic means responsive to both of said overflow outputs and connected to both of said clock enable inputs to enable a first one of said counters to be clocked by said angle signals only between presetting of both of said counters and the completion of counting in said first counter as indicated by a signal at the overflow output of said first counter, and to enable said second counter go be clocked by said angle signals only between completion of count of said first counter and completion of count of said second counter as indicated by signals at both said overflow outputs.