Muting signal generation circuit for an FM receiver
AssigneePioneer Electronic Corporation
InventorTatsuo Numata
Life of this patent
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Abstract
An improved muting signal generation circuit of an FM receiver of the type in which the deviation of an FM detection signal relative to a predetermined level is detected. When the deviation of the FM detected signal is above or below a predetermined value, a muting signal is generated. A band elimination filter is provided for eliminating the frequency components of an information signal contained in the FM detection signal. A detuning detection circuit detects detuning in response to the output of the band elimination filter. A muting signal generation circuit generates a muting signal in response to the detection output of the detuning detection circuit.
Claims10
In an FM receiver of the type having an FM detector, a muting circuit comprising:
- a band elimination filter means connected to said FM detector for eliminating the information content of the output of said FM detector and passing to an output thereof high frequency noise and the d.c. component in the FM detector output, and
- circuit means connected to the output of said band elmination filter means for generating a muting output signal in response to either one of said d.c. component and said noise being above a predetermined level.
A muting circuit for an FM receiver comprising:
- band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal;
- a complementary input circuit having an input coupled to an output of said band elimination filter means;
- first and second current mirror circuits coupled to said complementary input circuit;
- and
- an amplifier circuit coupled to respond to both said first and second current mirror circuits.
A muting circuit for an FM receiver comprising in combination:
- A. band elimination filter means, an input of said band elimination filter means being coupled to a source of a detected FM signal;
- and
- B. a combination detecting circuit, said combination detecting circuit comprising:
- (1) a complementary input circuit including a first NPN transistor and a first PNP transistor, said first NPN and said first PNP transistors having bases coupled to an output of said band elimination filter means and having emitters coupled to a source of a reference potential;
- (2) a first current mirror circuit including second and third PNP transistors, said second PNP transistor having a collector and a base coupled to the collector of said first NPN transistor and the base of said third PNP transistor and the emitter of said second PNP transistor being coupled to the emitter of said third PNP transistor and to a positive terminal of a power source;
- (3) a second current mirror circuit including second and third NPN transistors, said second NPN transistor having a collector and base coupled to the collector of said first PNP transistor and to the base of said third NPN transistor, the emitters of said second and third NPN transistors being coupled to a ground of said power source, and the collector of said third NPN transistor being coupled to the collector of said first NPN transistor;
- (4) an emitter follower circuit including a fourth NPN transistor having a base coupled to the collector of said third PNP transistor and one terminal of a first resistor, the second terminal of which is connected to ground, a collector coupled through a second resistor to said positive terminal and an emitter coupled through a third resistor to ground.
Dependencies are inferred from the claim text.