Drive control system for stepping motor

In an electronic timepiece having a standard frequency timebase signal source, a frequency divider circuit responsive to a timebase signal produced by said standard frequency timebase signal source for producing a unit time signal, drive circuit means for producing a drive signal, a stepping motor having a drive coil and a rotor, said stepping motor being periodically actuated by said drive signal to rotate said rotor through a predetermined angle, and time indicating means driven by said stepping motor for indicating time information, a drive control system for controlling said drive signal in accordance with a load torque applied to said stepping motor, comprising:

• control and detection circuit means coupled to said drive circuit means and said frequency divider circuit for detecting the amplitude of a detection signal voltage developed across said drive coil during a sampling interval of predetermined duration occurring after each periodic actuation of said stepping motor by said drive signal, said control and detection circuit means operating in a normal detection status when a relatively low load torque is applied to said stepping motor and in an increased drive detection status when a relatively high load torque is applied to said stepping motor, said normal detection status being characterized in that a drive signal of relatively low power is applied to said drive coil and in that a transition to said increased drive detection status is executed by said control and detection circuit means when the amplitude of said detection signal falls below a first predetermined amplitude, and said increased drive detection status being characterized in that a drive signal of relatively high power is applied to said drive coil and in that a transition to said normal detection status is executed by said control and detection circuit means when the amplitude of said detection signal goes above a second predetermined amplitude.

An electronic timepiece comprising, in combination:

• a standard frequency oscillator for providing a timebase signal;
• a frequency divider circuit responsive to said timebase signal for providing a unit time signal and a plurality of timing signals;
• a normal drive input signal generating circuit responsive to said unit time signal for providing a normal drive input signal;
• an increased drive input signal generating circuit responsive to said unit time signal for providing an increased drive input signal comprising a pulse train of greater pulse width than that of pulses in said normal drive input signal;
• selector circuit means coupled to receive said normal drive input signal and said increased drive input signal;
• an interruption signal generating circuit responsive to a timing signal from said frequency divider circuit for producing an interruption signal, comprising a pulse of short duration which is generated after a predetermined time interval following the leading edge of a pulse of said normal drive input signal and said increased drive input signal;
• a gate circuit coupled to receive said normal drive signal and said increased drive input signal from said selector circuit and further coupled to receive said interruption signal;
• a stepping motor having a drive coil;
• time indicating means driven by said stepping motor for indicating time information;
• a drive circuit having output terminals coupled to said stepping motor drive coil and having first input terminals coupled to receive said normal drive input signal and said increased drive input signal from said selector circuit and second input terminals coupled to an output terminal of said circuit;
• a sampling signal generating circuit responsive to a timing signal from said frequency divider circuit for producing a sampling signal comprising a pulse of short duration synchronized with said interruption signal and overlapping said interruption signal pulse to at least a partial extent;
• a detection circuit having input terminals coupled to said drive coil, said detection circuit being responsive to said sampling signal for detecting a detection signal voltage generated by said drive coil when an open-circuit condition is established between the terminals thereof by said drive circuit in response to said interruption signal applied through said gate circuit during a sampling interval of duration defined by the pulse width of a pulse of said sampling signal, said detection circuit being responsive to an increase of said detection signal voltage above a predetermined detection threshold during said sampling interval for producing a status control signal at a first logic level potential, and being responsive to said detection signal voltage being below said predetermined detection threshold level for producing said status control signal at a second logic level potential;
• said selector circuit being responsive to said first logic level state of said status control signal for applying said normal drive input signal to said drive circuit and responsive to said second logic level state of said status control signal for applying said increased drive input signal to said drive circuit, said sampling signal generating circuit being responsive to said first logic level of the status control signal for producing sampling signal pulses at a first predetermined timing after the leading edge of each pulse of said normal drive input signal and responsive to said second logic level state of the status control signal for producing sampling pulse at a second predetermined timing after the leading edge of each pulse of said increased drive input signal, and said interruption signal generating circuit being responsive to said first and second logic level states of said status control signal for producing interruption signal pulses at a first and second predetermined timing respectively following the leading edge of a pulse of said normal drive input signal and said increased drive input signal respectively.

An electronic timepiece comprising, in combination:

• a standard frequency oscillator circuit for providing a timebase signal;
• a frequency divider circuit responsive to said timebase signal for producing a unit time signal and a plurality of timing signals;
• a selector circuit coupled to receive timing signals from said frequency divider circuit and controlled by a status control signal, for producing a modulation signal of relatively low duty cycle when said status control signal is at a first logic level potential and producing a modulation signal of relatively high duty cycle when said status control signal is at a second logic level potential, said modulation signal comprising a pulse train of substantially higher frequency than said unit time signal;
• a first gate circuit for receiving said modulation signal and said unit time signal, for thereby producing a drive input signal comprising periodically repeated bursts of pulses, by modulating said unit time signal with said modulation signal;
• a stepping motor having a drive coil;
• time indicating means driven by said stepping motor for indicating time information;
• circuit means coupled to receive said timing signals from said frequency divider circuit, for producing an interruption signal comprising a pulse of short duration generated after a predetermined time interval following each of said drive input signal pulse bursts, and for producing a sampling signal comprising a pulse of short duration synchronized with said interruption signal and at least partially overlapping a pulse of said interruption signal in time;
• a second gate circuit coupled to receive said drive input signal and said interruption signal;
• a drive circuit having first input terminals coupled to receive said drive input signal and second input terminals coupled to the output of said second gate circuit, and having output terminals coupled across said drive coil of the stepping motor, said drive circuit being responsive to said drive input signal for applying a drive signal of relatively low power to said drive coil when said modulation signal is of relatively low duty cycle and a drive signal of relatively high power to said drive coil when said modulation signal is of relatively high duty cycle, said drive circuit being further responsive to the output of said second gate circuit for establishing a short-circuit condition across said drive coil from the termination of each pulse burst of said drive signal to the start of a succeeding interruption signal pulse, and from the termination of an interruption signal pulse to the start of a succeeding drive signal pulse burst, and also for establishing an open-circuit condition across said drive coil during each of said interruption signal pulses;
• a detection circuit having first and second input inverters coupled to said drive coil for detecting a detection signal produced by said drive coil when open-circuited by said drive circuit, said first input inverter producing an output signal when said detection signal amplitude exceeds a first predetermined threshold voltage thereof and said second input inverter producing an output signal when said detection signal amplitude exceeds a second predetermined threshold voltage thereof, said second threshold voltage being higher than said first threshold voltage, a second selector circuit coupled to receive said first and second input inverter output signals, being responsive to said first and second logic level states of said status control signal for transferring said output signals of said first and second input inverters respectively to an output terminal thereof, a third selector gate circuit coupled to receive the output of said second selector circuit and controlled by said sampling pulse for transferring output signals from said second selector circuit to an output terminal thereof during a sampling interval defined by the duration of a sampling signal pulse, and a flip-flop circuit for producing said status control signal, said flip-flop circuit being responsive to the output of said third selector circuit for producing said status control signal at said first logic level potential while output signals are produced from said third selector circuit and producing said status control signal at said second logic level potential in the absence of output signals being produced from said third selector circuit.