Signal processor for digital echo canceller

A system for multiplying first and second A-law encoded binary factors, the first factor having an exponent x.sub.e, a mantissa x.sub.m and a sign bit and the second factor having an exponent h.sub.e, a mantissa h.sub.m and a sign bit, comprising first circuit means for receiving the mantissas at inputs thereto and for generating at outputs therefrom the quantities (x.sub.m +1) and (h.sub.m +1) and active carry bits x.sub.c and h.sub.c whenever the respective quantity equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;

• multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P.sub.m ;
• second circuit means for receiving said quantities and controllable to generate an output signal S.sub.m which equals either zero, one of said quantities or a summation of both of said quantities;
• a first adder circuit for generating at an output therefrom a summation .SIGMA..sub.m of signals at inputs thereto, said first adder circuit receiving at its inputs said signals P.sub. m and S.sub.m, and one of said adder circuit and said second circuit means providing 2.sup.4 weighting for said signal S.sub.m in said summation signal .SIGMA..sub.m ;
• a second adder circuit for generating at an output therefrom a summation signal .SIGMA..sub.e of signals at inputs thereto, said second adder circuit receiving at its inputs the exponents x.sub.e and h.sub.e ;
• a decoder circuit for receiving the exponents x.sub.e and h.sub.e and said carry signals x.sub.c and h.sub.c, said decoder circuit having outputs which are selectively rendered active in accordance with the values of x.sub.e, h.sub.e, x.sub.c and h.sub.c, wherein two of said outputs E.sub.c1 and E.sub.c2 are applied to inputs to said second adder circuit, another two of said outputs x.sub.i and h.sub.i are applied to said second circuit means to control the same, and one output 2.sup.8 is applied to one of said second circuit means and said first adder circuit to cause the introduction, when said output is active, of 2.sup.8 into said signal .SIGMA..sub.m ;
• and shifter circuit means having data inputs for receiving said first adder circuit output signal .SIGMA..sub.m and shift control inputs for receiving said second adder circuit output signal .SIGMA..sub.e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal .SIGMA..sub.m and generating said signal .SIGMA..sub.m at selected ones of said outputs in accordance with the value of said signal .SIGMA..sub.e.

A system for multiplying first and second A-law encoded binary factors wherein the first factor has a non-zero exponent x.sub.e, a mantissa x.sub.m and a sign bit and the second factor has a non-zero exponent h.sub.e, a mantissa h.sub.m and a sign bit, comprising first circuit means for receiving the mantissas at inputs thereto and for generating at outputs therefrom the quantities (x.sub.m +1) and (h.sub.m +1) and active carry bits x.sub.c and h.sub.c whenever the respective quantity equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;

• multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P.sub.m ;
• a first binary adder circuit for receiving said quantities and for generating a summation signal S.sub.m of the same;
• a second binary adder circuit for generating at an output therefrom a summation signal .SIGMA..sub.m of signals at inputs thereto, said second binary adder receiving said signals P.sub.m and S.sub.m at inputs thereto and one of said first and second binary adder circuits providing 2.sup.4 weighting for said signal S.sub.m in said signal .SIGMA..sub.m ;
• means for applying a 2.sup.8 input signal to an input to one of said first and second binary adder circuits so that said signal .SIGMA..sub.m equals (P.sub.m +2.sup.4 S.sub.m +2.sup.8);
• a third binary adder circuit for receiving at inputs thereto the exponents x.sub.e and h.sub.e and signals representative of said carry bits x.sub.c and h.sub.c and for generating at an output therefrom a summation signal .SIGMA..sub.e which equals the sum of the exponents plus one (+1) for each active carry bit;
• and shifter circuit means having data inputs for receiving said signal .SIGMA..sub.m and shift control inputs for receiving said signal .SIGMA..sub.e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal .SIGMA..sub.m and generating said signal .SIGMA..sub.m at selected ones of its outputs in accordance with the value of said signal .SIGMA..sub.e.

A system for multiplying first and second A-law encoded binary factors wherein the first factor has an exponent x.sub.e equal to zero, a mantissa x.sub.m having a value less than the maximum step value for the range of A-law encoding used and a sign bit, and the second factor has a non-zero exponent h.sub.e, a mantissa h.sub.m and a sign bit, comprising first circuit means for receiving the mantissa at inputs thereto and for generating at outputs therefrom the quantities (x.sub.m +1) and (h.sub.m +1) and an active carry bit h.sub.c whenever the quantity (h.sub.m +1) equals zero, which occurs whenever the mantissa h.sub.m has the maximum step value;

• multiplier circuit means for receiving said quantities and for multiplying the same to generate a product signal P.sub.m ;
• a first binary adder circuit for receiving at inputs thereto said quantity (x.sub.m +1) and said signal P.sub.m, said binary adder circuit providing 2.sup.4 weighting for said quantity (x.sub.m +1) and generating at an output therefrom a summation signal .SIGMA..sub.m equal to [P.sub.m +2.sup.4 (x.sub.m +1)];
• second circuit means for receiving the exponent h.sub.e and said carry bit h.sub.c at inputs thereto and for generating an output signal .SIGMA..sub.e equal to (h.sub.e +1) if the carry bit h.sub.c is inactive or (h.sub.e +2) if the carry bit h.sub.c is active;
• and shifter circuit means having data inputs for receiving said signal .SIGMA..sub.m and shift control inputs for receiving said signal .SIGMA..sub.e, said shifter circuit having a plurality of outputs greater in number than the number of bits in said signal .SIGMA..sub.m and generating said signal .SIGMA..sub.m at selected ones of its outputs in accordance with the value of said signal .SIGMA..sub.e.

A method of multiplying first and second A-law encoded binary factors, wherein one factor represents a signal that causes an echo on an echo path for a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein the first factor has a non-zero exponent x.sub.e, a mantissa x.sub.m and a sign bit and the second factor a non-zero exponent h.sub.e, a mantissa h.sub.m and a sign bit, comprising the steps of incrementing each of the mantissas to generate the quantities (x.sub.m +1) and (h.sub.m +1);

• generating a carry bit x.sub.c and h.sub.c whenever a respective quantity (x.sub.m +1) and (h.sub.m +1) equals zero, which occurs whenever the respective mantissa equals the maximum step value for the range of A-law encoding used;
• multiplying said quantities to generate a product P.sub.m thereof;
• adding said quantities to generate a summation S.sub.m of the same;
• weighting said summation S.sub.m by 2.sup.4 to generate 2.sup.4 S.sub.m ;
• adding said weighted summation 2.sup.4 S.sub.m and said product P.sub.m to generate a summation .SIGMA..sub.m thereof;
• incrementing said summation .SIGMA..sub.m by 2.sup.8 so that the same equals (P.sub.m +2.sup.4 S.sub.m +2.sup.8);
• adding the exponents and incrementing the same by plus one (+1) for each generated carry bit x.sub.c and h.sub.c to generate a summation .SIGMA..sub.e ;
• and shifting said summation .SIGMA..sub.m by a number of bit places equal to the value of said summation .SIGMA..sub.e to generate the product of the factors.

A method of multiplying first and second A-law encoded binary factors, wherein one factor represents a signal that causes an echo on an echo path of a transmission system and the other the impulse response of the system, in order to generate an echo estimate for subtraction from the echo on the echo path, and wherein the first factor has an exponent x.sub.e which equals zero, a mantissa x.sub.m having a value less than the maximum step value for the range of A-law encoding used and a sign bit, and the second factor has a non-zero exponent h.sub.e, a mantissa h.sub.m and a sign bit, comprising the steps of incrementing each of the mantissas to generate the quantities (x.sub.m +1) and (h.sub.m +1);

• generating a carry bit h.sub.c whenever the mantissa h.sub.m has the maximum step value;
• multiplying said quantities to generate a product P.sub.m thereof;
• weighting said quantity (x.sub.m +1) by 2.sup.4 to generate 2.sup.4 (x.sub.m +1);
• adding said weighted quantity 2.sup.4 (x.sub. m +1) and said product P.sub.m to generate a summation .SIGMA..sub.m thereof;
• generating an output signal .SIGMA..sub.e which equals (h.sub.e +1) if said carry bit h.sub.c is inactive or (h.sub.e +2) if said carry bit h.sub.c is active;
• and shifting said summation .SIGMA..sub.m by a number of bit places equal to the value of said summation .SIGMA..sub.e to generate the product of the factors.