Binary input/output processing in a digital computer using assigned times for input and output data
AssigneeFord Motor Company
InventorsBrian S. Edelman, Ralph L. Robinson, Jr.
Life of this patent
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Abstract
A digital computer has a master clock for generating master clock pulses at a first frequency and has a counter for counting secondary clock pulses having a frequency less than the frequency of the master clock pulses. The secondary clock pulses are counted and used in the assignment of real times to bytes of input data, and in the comparison of real times with desired output times assigned to binary output data. The input data preferably is placed in a FIFO stack and the output data in a self-sorting stack. The sorting in the output stack occurs between changes in count in the counter containing the secondary clock pulses.
Claims9
In a digital computer that has a master clock for generating master clock pulses at a first frequency and that uses binary input data comprising a plurality of bits of information to produce binary output data in response to a program operating at least in part on one or more bits of the binary input data, improved processing of both the input and output data comprising the steps of:
- (a) generating secondary clock pulses having a frequency that is less than the frequency of the master clock pulses;
- (b) counting secondary clock pulses in a counter;
- and
- (c) using the count of the secondary clock pulses in the assignment of real time to bytes to input data and in the comparison of real times with desired output times assigned to binary output data.
In a digital computer that has a master clock for generating master clock pulses at a first frequency and that uses binary input data comprising a plurality of bits of information to produce binary output data in response to a program operating at least in part on one or more bits of the binary input data, improved processing of both the input and output data comprising the steps of:
- (a) generating secondary clock pulses having a frequency that is less than the frequency of the master clock pulses;
- (b) counting secondary clock pulses in a counter;
- (c) when a transition from one state to another of at least one of the bits of binary input data occurs, assigning to a byte containing the bit that has undergone transition a real-time type equal of proportional to the count of secondary clock pulses in the counter as of the time of occurrence of the transition;
- (d) assigning to a bit or byte of output data to be outputted by the digital computer a desired-output-time byte equal or proportional to a count of secondary clock pulses that subsequently will occur in the counter;
- (e) repetitively comparing the desired-output-time byte with bytes equal or proportional to the changing count of the secondary pulse counter;
- and
- (f) upon a predetermined result of the comparison of step (e) above, making available as an output the bit or byte of output data to which the desired-output-time byte was assigned.
Dependencies are inferred from the claim text.