US 4,283,235 A · Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation

Abstract

A process is described which combine polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means. This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Claims7

Dependent claims

A method for achieving isolation of integrated circuits comprising:

depositing a layer of oxide on a silicon substrate leaving open areas on which devices are to be subsequently made over the exposed silicon substrate,
growing simultaneously a layer of polycrystalline silicon on the oxide regions and a layer of epitaxial silicon on the exposed silicon regions of the substrate.
selectively forming a thick oxide layer on the surface of said polycrystalline and said epitaxial silicon layers leaving open those regions of the polycrystalline layer where resistors are to be made and those regions of the epitaxial silicon where junction devices are to be made,
the thickness of the oxide being such that the bottom of the oxide extends below the junction depth of junctions to be subsequently formed in said epitaxial silicon open regions and less than the thickness of the epitaxial layer, and
forming said junction devices in said epitaxial layer open regions,
at least one junction abutting the thick oxide layer beneath the surface of the epitaxial silicon,
whereby said oxide forms an oxide isolation between the junctions and said polysilicon layer surrounding the epitaxial silicon.

4 more elements

A method for achieving isolation of the silicon islands of integrated circuits comprising:

forming a first layer of oxide on a silicon substrate,
etching away areas of this oxide to form an oxide mask leaving open areas on which devices are to be subsequently made over the exposed silicon substrate,
forming buried collectors in such etched areas,
thinning said oxide mask,
simultaneously growing epitaxial silicon islands on said exposed silicon and polycrystalline silicon on said oxide,
depositing a layer of silicon nitride and masking and etching said layer of silicon nitride leaving unmasked the portions of said islands contiguous to said polysilicon surface and also any region of said island to be used for oxide isolation between impurity junctions.
etching the exposed silicon to a predetermined depth,
oxidizing the exposed silicon, the depth of said silicon etching and the thickness of said oxide being such that the top of said oxide is substantially co-planar with the top surface of the masked silicon islands and the bottom of the oxide extends below the junction depth of junctions to be subsequently formed in said epitaxial silicon islands,
removing said silicon nitride mask on the surface of the silicon islands to provide an exposed epitaxial silicon surface,
forming junction devices in said island surfaces.

7 more elements

Dependencies are inferred from the claim text.

Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation

Life of this patent

Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation

Life of this patent

Abstract

Claims7