CMOS process
AssigneeIntel Corporation
InventorsKenneth K. Yu, Mark T. Bohr, Mark B. Seidenfeld
Life of this patent
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Abstract
A CMOS Process for fabricating channel stops which are substantially formed as a by-product of growing a field oxide is described. A p-type region is formed at an edge (or edges) of an n-type well through an opening in a silicon nitride layer. An oxide is grown at the opening. As the oxide grows, n-type dopant from the n-type well accumulates at the edge of the oxide, forming a more highly doped n-type region. Simultaneously, an adjacent p-type region is formed under the oxide from the p-type dopant. The process also permits easy fabrication of a buried contact to the p-channel device thus eliminating the need for a metal contact when forming a bistable circuit.
Claims11
In the fabrication of CMOS integrated circuits, a process for forming a channel stop in a substrate, which includes an n-type region and a silicon nitride layer, comprising the steps of:
- defining an opening through said silicon nitride layer, said opening being formed at a peripheral area of said n-type region;
- doping said substrate with a p-type dopant through said opening;
- and
- forming an oxide on said substrate at said opening, such that a first region is formed from accumulated n-type dopant from said n-type region and a second region is formed adjacent to said first region from p-type dopant from said doping step;
- whereby said first and second regions form a channel stop.
In the fabrication of CMOS integrated circuits, a process for forming an isolation region in a substrate comprising the steps of:
- forming an n-type well in said substrate;
- forming a layer of silicon nitride on said substrate;
- defining an opening in said silicon nitride, said opening overlying a portion of said well and a portion of said substrate adjacent to said well;
- doping said substrate through said opening with a p-type dopant;
- and
- forming an oxide on said substrate at said opening such that said formation of said oxide causes an accumulation of n-type dopant from said well under said oxide adjacent to a p-type region formed under said oxide,
- whereby said n-type region and adjacent p-type region under said oxide form an isolation region.
A CMOS process for forming a p-channel transistor with an integral buried contact and channel stop, comprising the steps of:
- forming an n-type well in a substrate;
- doping a first region with a p-type dopant at the periphery of said n-type well;
- growing an oxide at said first region so as to form a channel stop comprising adjacent n-type and p-type regions;
- forming spaced-apart, p-type source and drain regions in said substrate within said n-type well for said p-channel transistor, one of said source and drain regions being adjacent to said n-type region of said channel stop;
- forming a polysilicon layer doped with an n-type dopant on said substrate, said polysilicon layer contacting one of said source and drain regions so as to form an n-type region within the said one of said source and drain regions;
- and
- pattering said polysilicon layer to form a gate member between said spaced-apart source and drain regions and a line in contact with the said one of said source and drain regions;
- whereby a p-channel transistor with an integral buried contact and channel stop is fabricated.
Dependencies are inferred from the claim text.