Mini-programmable controller

An improved digital controller of the type having an I/O interface responsive to status data for controlling devices on a machine, and having means for coupling status data between a main memory and the I/O interface, wherein the improvement comprises:

• a main memory that stores controller-type instructions and status data, each controller-type instruction including an untranslated operation code and the address of a status data operand;
• interpreter memory means for storing machine instructions organized in interpreter routines, each interpreter routine being associated with a translated operation code;
• translating memory means for storing translated operation codes at a first set of addresses and for storing mapping data at a second set of addresses, each word of mapping data being identical to a portion of its respective address in the second set of addresses, the translating memory means having a plurality of address inputs coupled to the main memory to receive data therefrom, and having a control input for receiving a control signal;
• processor means coupled to both the main memory and the control input on the translating memory means, for generating an untranslated operation code and a control signal at the inputs of the translating memory means to read a translated operation code therefrom, the processor means also being coupled to the interpreter memory means and being responsive to the translated operation code to execute an associated interpreter routine.

An improved digital controller of the type having an I/O interface responsive to status data for controlling devices on a machine, and having means for coupling status data between a main memory and the I/O interface, wherein the improvement comprises:

• first means for entering controller-type instructions and status data into the controller, each controller-type instruction including an untranslated operation code and the address of a status data operand;
• second means coupled to the first means for storing translated operation codes at a first set of addresses and for storing mapping data at a second set of addresses, each word of mapping data being identical to a portion of its respective address in the second set of addresses, the second means having a plurality of address inputs receiving an untranslated operation code, and having a control input for receiving a control signal;
• third means for storing machine instructions organized in interpreter routines, each interpreter routine being associated with a translated operation code;
• fourth means coupled to both the first means and the control input on the second means, for generating an untranslated operation code and a control signal at the inputs of the second means to read a translated operation code therefrom;
• and
• fifth means coupled to the second means and the third means and responsive to the translated operation code read from the second means to execute an associated interpreter routine in the third means.

A digital controller which comprises:

• an address bus;
• a data bus;
• I/O interface means for coupling input status data and output status data between the data bus and devices on a controlled machine;
• interpreter memory means for storing machine instructions organized in interpreter routines that perform controller-type operations;
• main memory means, coupled to the address bus, for storing control program instructions that include untranslated operation codes and operand addresses, and for storing operand status data;
• a translator memory, coupled to the data bus and coupled to the main memory means to be addressed by data read from the main memory means, the translator memory storing translated operation codes at a first set of addresses and storing mapping data at a second set of addresses;
• and
• processor means coupled to the address bus, coupled to the data bus, and coupled to the interpreter memory means, for coupling translated operation codes and associated operand addresses from the main memory means together with control signals to the translator memory,
• wherein the processor means is responsive to machine instructions stored in the interpreter memory means to read a translated operation code and a mapped operand address from the translator memory, and is further responsive to execute an interpreter routine to perform the operation directed by the translated operation code on a selected operand.

A digital controller which comprises:

• I/O interface means for operating a plurality of control devices on a machine;
• memory means for storing data representing the status of the controlled devices and for storing a control program of controller-type instructions;
• processor means for generating addresses to read control program instructions, for executing the control program instructions to manipulate the status data, and for coupling status data between the memory means and the I/O interface means;
• error checking means coupled to the memory means for detecting an error in data coupled from the memory means during the execution of the control program;
• error status means coupled to the error checking means for signaling that an error has been detected;
• and
• error storage means, coupled to the memory means, coupled to the processor means, coupled to the error status means and responsive to an error signal from the error status means, for receiving and storing both the erroneous data from the memory means and the address generated by the processor means to read such erroneous data.