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US 4,281,449 AGranted
Method for qualifying biased burn-in integrated circuits on a wafer level
AssigneeHarris Corporation
InventorsKenneth A. Ports, Thomas R. St. Clair
Life of this patent
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Abstract
Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.
Claims10
A method for qualifying biased burn-in integrated circuits at a wafer level comprising:
- forming a first and a second discrete conductor on said wafer, each connected to each die on said wafer and at least one of said conductors being connected to each die by a fusible element;
- electrically biasing said conductors;
- heating said wafer at a high, burn-in temperature while electrically biased;
- testing the condition of the fusible elements and marking defectively connected dice;
- removing said conductors;
- and
- testing the circuitry on said dice and marking defective dice.
4 more elements
A method for qualifying biased burned-in integrated circuits at the wafer level comprising:
- forming a first plurality of conductors on a wafer connected to a first electrode;
- forming a second plurality of connectors on said wafer connected to a second electrode;
- interconnecting each dice on said wafer to at least one conductor of each of said first and second plurality of conductors by at least one fusible element per die;
- electrically biasing said dice on said wafer via said electrodes;
- heating said wafer at a sufficiently high temperature for a sufficient amount of time to perform a burn-in while electrically biased;
- testing said fusible elements and marking defectively connected dice;
- and
- testing the circuit on said dice and marking defective circuits.
5 more elements
Dependencies are inferred from the claim text.