US 4,280,212 AGranted

Multiplexing system for a solid state timing device

AssigneeSolid State Scientific Corporation

InventorsStephen A. Ransom, Jere W. Hohmann, Clement Nahmias

Life of this patent

Estimating the term…

Loading patent…

Abstract

A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.

Claims10

Dependent claims

A solid state timing device having a chain of counters for displaying time information on a display comprising

decoder means for operating said display,
multiplexing means for coupling selected counters to said decoder means, said multiplex means having a plurality of multiplex sections,
each multiplex section including a common bus having a plurality of data transmission channels, a plurality of MOS devices of only a first type forming each of said channels, a complementary MOS device of a second type coupled to said common bus providing a complementary function with respect to said first type of MOS devices to establish predetermined operating voltage levels of the bus for the logic states,
means providing each multiplex section a first reference potential coupled to each of said channels and a second reference potential coupled to said complementary MOS device whereby said complementary MOS device operates as a low impedance pull-up resistor between said common bus and said second reference potential, and
signalling means having a substantially short duty cycle coupled to a switching terminal of said complementary MOS device of each multiplex section for turning on said device and establishing for a substantially short period of time a predetermined operating voltage level on said common bus of substantially (1) said first reference potential when all the MOS devices of any channel are turned on and (2) said second reference potential when less than all the MOS devices of any channel are turned on.

2 more elements

A solid state timing device having a chain of counters for displaying time information on a display comprising

decoder means for operating said display,
multiplexing means for coupling selected counters to said decoder means, said multiplex means having a plurality of multiplex sections,
each multiplex section including a common bus having a plurality of data transmission channels, a plurality of MOS devices of only a first type forming each of said channels, and a complementary MOS device of a second type coupled to said common bus providing a complementary function with respect to said first type of MOS devices to establish predetermined operating voltage levels of the bus for the logic states,
each multiplex section including bistable latching means coupled between said common bus and said decoder means, and
means providing for each multiplex section a first reference potential coupled to each of said channels and a second reference potential coupled to said complementary MOS device whereby said complementary MOS device operates as a low impedance pull-up resistor between said common bus and said second reference potential.

2 more elements

Dependencies are inferred from the claim text.