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AssigneeCSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
InventorGiancarlo Babini
Estimating the term…
A storage capacitor of a sample-and-hold circuit, e.g. as used in a converter for the digitization of signal amplitudes in a PCM telephone system, is provided with a zero-setting gate comprising two parallel branches that include a first and a second transistor which are respectively saturated during a cancellation phase and a discharge phase of a resetting interval following a sampling period. The first transistor lies in series with a d-c source whose voltage substantially exceeds the maximum amplitude of signals of the same polarity to be stored on that capacitor whereby the latter acquires a charge within a range considerably narrower than the spread of positive and negative signal amplitudes. The second transistor then short-circuits the capacitor so charged, leaving a residual charge of predetermined polarity subject to still smaller variations in magnitude.
A method of periodically dissipating the charge of a storage capacitor charged in the interim with message samples within a predetermined range of positive and negative signal amplitudes, comprising the steps of:
A circuit arrangement for periodically dissipating the charge of a storage capacitor provided with intermittently conducting gate means for charging said capacitor with message samples within a predetermined range of positive and negative signal amplitudes between resetting intervals, comprising:
Dependencies are inferred from the claim text.