Latch circuit operable as a D-type edge trigger

A shift register latch circuit for use in an integrated circuit conforming to Level Sensitive Scan Design (LSSD), said shift register latch circuit comprising:

• a first AND/INVERT circuit having a first input for receiving a SCAN IN input, a second input for receiving a first clock pulse train, and an output;
• a second AND/INVERT circuit having a first input for receiving a data input, a second input for receiving a second clock pulse train, and an output;
• a third AND/INVERT circuit having a first input for receiving the complement of said second clock pulse train, a second input for receiving the complement of said first clock pulse train, a third input, and an output;
• an Inverter circuit having an input and output;
• a fourth AND/INVERT circuit having a first input connected in common to said output of said first AND/INVERT circuit, said output of said second AND/INVERT circuit, said output of said third AND/INVERT circuit and said input of said Inverter circuit, a second input, and an output;
• a fifth AND/INVERT circuit having a first input connected in common to said output of said Inverter circuit and said third input of said third AND/INVERT circuit, a second input connected in common with said second input of said fourth AND INVERT circuit for receiving a third clock pulse train, and an output;
• a sixth AND/INVERT circuit having a first input connected to said output of said fourth AND/INVERT circuit, a second input, and an output;
• and
• a seventh AND/INVERT circuit having a first input connected to said output of said sixth AND/INVERT circuit, a second input connected to said output of said fifth AND/INVERT circuit and an output connected to said second input of said sixth AND/INVERT.