Binary analog-digital converter

A binary analog-digital converter in which the analog quantity to be converted into a binary digital signal is represented by a current which lies between the minimum current and the maximum current that can be converted comprising:

• an input stage;
• a number of conversion stages equal to the number of n digital-signal bits required;
• and
• an output stage;
• each of said (n+2) stages of the order 0, 1, 2, . . . , i, . . . n-1, n, n+1 comprising two separate transmission channels, i.e. a comparison channel and a reference channel, all the comparison channels of the (n+2) stages being connected in series, all the reference channels of said (n+2) stages also being connected in series;
• transition circuits being included between the comparison channel of each conversion stage and that of the next stage and between the reference channel of each conversion stage and that of the next stage;
• the comparison channel of the input stage being adapted to transfer an input current to the comparison channel of the next stage and the reference channel being of the input stage adapted to transfer a reference current, which is equal to a fraction of the maximum current, to the reference channel of the next stage, the difference between said input current and the reference current constituting a current which is representative of the analog quantity to be converted into a binary digital signal;
• in each of the n conversion stages of the order 1, 2, 3, . . . , i, . . . , n-1, n, the comparison channel of the stage of the order i being adapted to transfer a comparison current, which comprises at least the input current, to the comparison channel of the following stage, and the reference channel of said stage of the order i being adapted to transfer a reference current equal to a fraction of the maximum current to the reference channel of the next stage;
• each of the n conversion stages of the order 1, 2, 3, . . . , i, . . . , n-1, n, comprising a comparator which, depending on the two possible results of a comparison between the two currents which are respectively applied to the comparison and refernce channels of the conversion stage of the order i by said channels of the preceding stage, is adapted to determine whether the logic level of the bit associated with said stage of the order i has one, or conversely the other, of the two values which said bit may assume and by means of the two currents compared in the conversion stage of the order i and an auxiliary current which is equal to a fraction of the maximum current and which is applied to said stage of the order i with the aid of a corresponding auxiliary current source, to switch such a current to the comparison and reference channels of the next stage that, if and only if one bit is left whose logic level has not yet been determined, the comparator of the following stage corresponding to said bit whose level is still undetermined can then compare the input current with the sum, or conversely the difference, of the reference current applied to said conversion stage of the order i by the reference channel of the preceding stage and the auxiliary current applied to said stage of the order i with the aid of the corresponding auxiliary current source, said sum and said difference in all cases lying between the minimum current and the maximum current that can be converted, each comparison between two currents being effected by a comparison between two voltages which are proportional to said currents, and the current switching under control of the comparator being adapted to make the currents in the comparison and reference channels equal, even if there is no longer a bit whose logic level has not yet been determined;
• in the output stage the comparison and reference channels are adapted to respectively receive the currents which are transferred by the comparison and reference channels of the last conversion stage of the order n;
• each comparison between two voltages being realized by a comparison between potential difference across two equal resistors which are each included in one channel of each conversion stage;
• depending on the two possible results of the comparison between the reference current applied to the reference channel of said stage of the order i by that of the preceding stage and the current applied to the comparison stage of the same stage of the order i by that of the preceding stage, the comparator of each conversion stage of the order is adapted to determine whether the logic level of the bit corresponding to said stage of the order i has the one, or conversely the other, of the two values which said level may assume, and to switch the auxiliary current which also corresponds to said stage of the order i to the comparison channel or, conversely, the reference channel of the following stage;
• and
• the comparator of each conversion stage of the order i, in accordance with one or the other of the two possible results of the comparison between the reference current applied to the reference channel of said stages of the order i by that of the preceding stage and the current applied to the comparison channel of said stage of the order i by that of the preceding stage, is adapted to determine whether the logic level of the bit corresponding to said stage of the order i has the one or, converely, the other of the two values which said level may assume, and to switch said reference current to the reference channel of the following stage and the sum of said current, applied to the comparison channel of said stage of the order i by that of the preceding stage, and the auxiliary current, which also corresponds to said stage of the order i, to the comparison channel of the following stage, or, conversely, to switch the current applied to the comparison channel of said stage of the order i by the comparison channel of the preceding stage to the reference channel of the following stage and the sum of said reference current and the auxiliary current to the comparison channel of the following stage.