MOS decoder logic circuit having reduced power consumption

A decoder circuit comprising:

• a logic gate circuit consisting of a common load MISFET connected to a first reference potential terminal, and a plurality of driver MISFET's connected in parallel with each other to receive address signals through their respective gates;
• an inverter circuit consisting of a load MISFET connected to said first reference potential terminal, and a driver MISFET for receiving output signals of said logic gate circuit through the gate;
• a first switching MISFET having first and second terminals, said first terminal being connected to said first reference potential terminal to receive the control signals through the gate;
• a first MISFET connected between a second terminal of said first switching MISFET and an output terminal to receive the output signals of said logic circuit through the gate;
• a second MISFET connected between said output terminal and a second reference potential terminal to receive the output signals of said inverter circuit through the gate;
• and
• a second switching MISFET which receives, through the gate, control signals for connecting the plurality of driver MISFET's of said logic gate circuit and said driver MISFET of said inverter circuit to said second reference potential terminal.

A decoder circuit for MIS static memory circuit comprising;

• a plurality of decoder circuits, each of which having a logic gate circuit consisting of a common load MISFET connected to a first reference potential terminal and a plurality of driver MISFET's connected in parallel with each other to receive address signals through their respective gates, an inverter circuit consisting of a load MISFET connected to said first reference potential terminal and a driver MISFET for receiving the output signals of said logic gate circuit through the gate, a series circuit consisting of a first MISFET for receiving the output signal of said logic gate circuit through the gate and a second MISFET for receiving the output signal of said inverter circuit through the gate, a first switching MISFET which receives, through the gate, control signals for connecting driver MISFET's of said logic gate circuit and the driver MISFET of said inverter circuit to a second reference potential terminal, and an output terminal connected between said first MISFET and said second MISFET;
• and
• a second switching MISFET for receiving the control signals through the gate;
• wherein the first MISFET of each of the decoder circuits is connected to said first reference potential terminal via said second switching MISFET.