MOS/SOS Process
AssigneeIntel Corporation
InventorRichard D. Pashley
Life of this patent
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Abstract
An MOS process for fabricating multi-layer integrated circuits particularly suited for SOS fabrication is disclosed. Transistors are fabricated both on the substrate level and in an overlying polysilicon layer. Processing techniques for aligning source and drain regions with a buried gate are described. In one embodiment, a photoresist layer is exposed to light directed through the sapphire substrate, thereby employing the buried gate as a masking member. Laser annealing may be used to provide larger crystals of silicon in the polysilicon layer.
Claims17
A process for fabricating two MOS transistors having a common gate region on a substrate comprising the steps of:
- forming a gate region insulated from said substrate, said gate region having an oxide member disposed above said gate region and a silicon nitride member disposed above said oxide member;
- doping said substrate in alignment with said gate region to form first source and drain regions of a first MOS transistor;
- forming an oxide layer on said substrate, said silicon nitride member preventing substantial oxide formation on said gate region during the oxide formation step;
- doping said oxide layer and silicon nitride member;
- removing said silicon nitride member;
- forming a polysilicon layer over said oxide layer and said oxide member;
- and
- diffusing the dopant from said oxide layer into said polysilicon layer so as to form second source and drain regions of a second MOS transistor in said polysilicon layer in alignment with said common gate region,
- whereby two MOS transistors are formed in vertical alignment with one another.
A process for forming a second MOS transistor above a first MOS transistor, said first transistor being disposed on a silicon surface and including a gate region and a silicon nitride member disposed above said gate, comprising the steps of:
- growing an oxide layer on said silicon surface such that said silicon nitride member prevents any substantial oxide growth between said gate and said silicon nitride member;
- doping the upper surface of said oxide layer and said silicon nitride member;
- removing at least the doped portion of said silicon nitride member;
- forming a polysilicon layer over said substrate;
- and
- diffusing said dopant from said oxide layer into said polysilicon layer so as to form source and drain regions in said polysilicon layer in alignment with said gate,
- whereby a second MOS transistor is formed above said first MOS transistor.
A process for forming a second MOS transistor above a first MOS transistor, said first transistor being disposed on an epitaxial silicon layer formed on a transparent substrate, said first transistor including a gate region and a silicon nitride member disposed above said gate region, comprising the steps of:
- growing an oxide layer on said silicon layer such that said silicon nitride member prevents any substantial oxide growth between said gate region and said silicon nitride member;
- forming a polysilicon layer over said substrate above said oxide layer;
- forming a radiation sensitive layer on said polysilicon layer;
- exposing said radiation sensitive layer to radiation directed through said transparent substrate such that said radiation sensitive layer disposed above said gate region remains substantially unaffected by said radiation;
- removing said radiation sensitive layer so as to define a mask in alignment with said gate region;
- and
- doping said polysilicon layer to form source and drain regions in alignment with said gate region,
- whereby a second transistor is formed above said first transistor.
A process for forming a pair of complementary MOS transistors on a silicon surface comprising the steps of:
- forming a first gate oxide layer on said silicon surface;
- forming a first layer of polysilicon on said first oxide layer;
- forming a second gate oxide layer on said first polysilicon layer;
- defining a silicon nitride masking member on said second oxide layer;
- etching said second oxide layer and said first polysilicon layer to define a gate member and a second gate oxide member;
- forming first source and drain regions in said silicon surface with a first conductivity type dopant in alignment with said gate member;
- growing a third oxide layer over said silicon surface such that said silicon nitride member prevents any substantial growth of said second gate oxide;
- doping the upper surface of said third oxide layer and said silicon nitride member with a second conductivity type dopant;
- removing said silicon nitride member;
- forming a second layer of polysilicon over said third oxide layer;
- diffusing the dopant from said third oxide layer into said second polysilicon layer so as to form second source and drain regions in alignment with said gate,
- whereby a pair of complementary transistors are formed having source and drain regions in alignment with said gate.
Dependencies are inferred from the claim text.