US 4,272,760 AGranted

Self-calibrating digital to analog conversion system and method

AssigneeBurr-Brown Research Corporation

InventorsPaul R. Prazak, Theodore L. Williams

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Abstract

A digital to analog conversion system includes a memory for storing a plurality of correction codes corresponding to corrections required to compensate for inaccuracy in output currents of a main digital to analog converter (DAC) contained in the digital to analog conversion system. A plurality of the logic inputs applied to the inputs of the main DAC are also applied to the address inputs of the memory. A trim DAC having its inputs coupled to the data outputs of the memory converts the correction code stored in the addressed location of the memory into a correction current which is utilized externally of the main DAC to modify the net amount of output current available from the main DAC to compensate for inaccuracy of the unmodified output current. An output signal from a temperature sensor is connected to a digital number which is also applied to a plurality of the address inputs. Correction codes stored in locations addressable in response to the temperature sensor have values which effect adjustment of the correction current to compensate for inaccuracy of the output current due to temperature variations. A self-calibration system and method which updates the correction codes stored in the memory are also disclosed.

Claims16

Dependent claims

A method for automatically calibrating a first digital to analog converter, said first digital to analog converter including a plurality of digital inputs and an output terminal for producing an analog output signal, said method comprising the steps of:

(a) applying a first pattern of logic signals to the inputs of said first digital to analog converter and also applying at least a portion of said first pattern of logic signals to the address inputs of a memory for storing a plurality of correction codes;
(b) performing a digital to analog conversion of said first pattern of logic signals to produce a first output voltage;
(c) temporarily maintaining a first analog signal representative of said first output voltage;
(d) applying a second pattern of logic signals to the inputs of said first digital to analog converter and also applying a portion of said second pattern of logic signals to the address inputs of said memory;
(e) performing a digital to analog conversion of said second pattern of logic signals to produce a second output voltage;
(f) comparing said first analog signal to said second output voltage to produce a first difference signal;
(g) performing an analog to digital conversion of said first difference signal to produce a first digital word;
(h) computing a first correction code based on said first digital word;
(i) writing said first correction code into a first location of said memory determined by said first pattern of logic signals;
(j) applying said first pattern of logic signals to the inputs of the first digital to analog converter and also applying said portion of said first pattern of logic signals to the address inputs of said memory;
(k) performing a digital to analog conversion of said first pattern of logic signals to produce said first output current;
(l) fetching said first correction code from said first location of said memory, said first location being addressed by said portion of said first pattern of logic signals;
(m) performing a digital to analog conversion of said first correction code to produce a first correction current;
and
(n) adding or subtracting a predetermined proportion of said first correction current to or from said first output current to compensate for an error in said first output current, thereby producing a first corrected output current.

12 more elements

A system for automatically calibrating a first digital to analog converter, said first digital to analog converter including a plurality of digital inputs and an output terminal for producing an analog output signal, said system comprising in combination:

(a) a memory having a plurality of correction codes stored in a plurality of locations respectively addressable by means of the address inputs;
(b) digital input means for applying a first pattern of logic signals to the inputs of said first digital to analog converter and for applying at least a first portion of said first pattern of logic signals to the address inputs of said memory, whereby said first digital to analog converter produces a first output voltage;
(c) first conversion means for effecting performing a digital to analog conversion of said first pattern of logic signals by said first digital to analog converter to produce a first output current;
(d) first control means for effecting fetching a first correction code from a first location of said memory, the first location being addressed by said portion of said first pattern of logic signals;
(e) second conversion means for performing a digital to analog conversion of said first correction code to produce a first correction current;
(f) means for adding or subtracting a predetermined proportion of said first correction current to or from said first output current to correct an error in said first output current, thereby producing a first corrected output current;
(g) calibration means for entering said plurality of correction codes into said memory, said calibration means including
(i) first means for applying said first pattern of logic signals to the inputs of said first digital to analog converter and also to the address inputs of said memory, whereby said first digital to analog converter produces a first output voltage;
(ii) first signal means for producing and maintaining a first analog signal representative of said first output voltage;
(iii) second means for applying a second pattern of logic signals to the inputs of said first digital to analog converter and also to the address inputs of said memory, whereby said digital to analog converter produces a second output voltage;
(iv) second comparison means for comparing said first analog signal to said second output voltage to produce a first difference signal;
(v) third conversion means for performing an analog to digital conversion of said first difference signal to produce a first digital word;
(vi) computing means for computing said first correction code based on said first digital word;
and
(ix) second control means for effecting writing said first correction code into the location of said memory determined by said first pattern of logic signals.

12 more elements

(a) applying a first pattern of logic signals to the inputs of said first digital to analog converter and also applying at least a portion of said first pattern logic signals to the address inputs of a memory for storing a plurality of correction codes;
(a) performing a digital to analog conversion of said first pattern of logic signals to produce a first output voltage;
(c) performing a digital to analog conversion of a predetermined group of said first pattern of logic signals to produce a first offset signal;
(d) comparing said first offset signal to said first output voltage to produce a first difference signal;
(e) performing an analog to digital conversion of said first difference signal to produce a first digital word;
(f) applying a second pattern of logic signals to the inputs of said first digital to analog converter and also applying a portion of said second pattern of logic signals to the address inputs of said memory;
(g) performing a digital to analog conversion of said second pattern of logic signals to produce a second output voltage;
(h) comparing said first offset signal to said second output voltage to produce a second difference signal;
(i) performing an analog to digital conversion of said second difference signal to produce a second digital word;
(j) computing a first correction code based on the difference between said first and second digital words;
(k) writing said first correction code into a first location of said memory determined by said first pattern of logic signals;
(l) applying said first pattern of logic signals to the inputs of the first digital to analog converter and also applying said portion of said first pattern of logic signals to the address inputs of said memory;
(m) performing a digital to analog conversion of said first pattern of logic signals to produce said first output current;
(n) fetching said first correction code from said first location of said memory, said first location being addressed by said portion of said first pattern of logic signals;
(o) performing a digital to analog conversion of said first correction code to produce a first correction current;
and
(p) adding or subtracting a predetermined proportion of said first correction current to or from said first output current to compensate for an error in said first output current, thereby producing a first corrected output current.

14 more elements

(a) a memory having a plurality of correction codes stored in a plurality of locations respectively addressable by means of the address inputs;
(b) digital input means for applying a first pattern of logic signals to the inputs of said first digital to analog converter and for applying at least a first portion of said first pattern of logic signals to the address inputs of said memory, whereby said first digital to analog converter produces a first output voltage;
(c) first conversion means for effecting performing a digital to analog conversion of said first pattern of logic signals by said first digital to analog converter to produce a first output current;
(d) first control means for effecting fetching a first correction code from a first location of said memory, the first location being addressed by said portion of said first pattern of logic signals;
(e) second conversion means for performing a digital to analog conversion of said first correction code to produce a first correction current;
(f) means for adding or subtracting a predetermined proportion of said first correction current to or from said first output current to correct an error in said first output current, thereby producing a first corrected output current;
(g) calibration means for entering said plurality of correction codes in said memory, said calibration means including
(i) first means for applying said first pattern of logic signals to the inputs of said first digital to analog converter and also to the address inputs of said memory, whereby said first digital to analog converter produces a first output voltage;
(ii) third conversion means for performing a digital to analog conversion of a predetermined group of said logic signals of said first pattern to produce a first offset signal;
(iii) first comparison means for comparing said first offset signal to said first output voltage to produce a first difference signal;
(iv) fourth conversion means for performing an analog to digital conversion of said first difference signal to produce a first digital word;
(v) second means for applying a second pattern of logic signals to the inputs of said first digital to analog converter and also to the address inputs of said memory, whereby said first digital to analog converter produces a second output voltage;
(vi) second comparison means for comparing said first offset signal to said second output voltage to produce a second difference signal;
(vii) fifth conversion means for performing an analog to digital conversion of said second difference signal to produce a second digital word;
(viii) computing means for computing said first correction code based on the difference between said first and second digital words;
and
(ix) second control means for effecting writing said first correction code into the location of said memory determined by said first pattern of logic signals.

14 more elements

Dependencies are inferred from the claim text.