Speed control circuit for phase-locked loop motor drive systems

A speed control system for a motor comprising:

• means for generating a pulse signal having a frequency proportional to speed of said motor and a first voltage signal having a magnitude proportional to the speed of said motor;
• a frequency divider for generating an output signal having a frequency that is an integral submultiple of the frequency of an input signal to the divider;
• a frequency-to-voltage converter for generating a second voltage signal having a magnitude proportional to the output frequency of said frequency divider;
• a phase comparator for generating a phase differential signal representing a difference in phase between said pulse signal and the output of said frequency divider;
• a lowpass filter responsive to the output of said phase comparator;
• a voltage comparator for generating a voltage differential signal representing a difference in magnitude between said first and second voltage signals;
• a summing amplifier for combining said phase differential signal through said lowpass filter with said voltage differential signal for energizing said motor;
• a source for generating pulse signals at high and low reference frequencies;
• a bistable device responsive to the output of said frequency divider to assume a first binary state;
• a programmable counter responsive to said low frequency pulses and said first binary state for defining a desired time period, said counter having a resettable count value for counting said low frequency reference pulses in response to the presence of said first binary state, said counter controlling said bistable device to change to a second binary state in response to said count value to define said desired period;
• means for selectively generating a speed increment and a speed decrement command signal;
• and
• means for normally applying said low frequency reference pulse signal to said frequency divider;
• means responsive to said speed increment command signal for applying said high frequency reference pulse signal instead of said low frequency reference pulse signal to said frequency divider during said defined period, and means responsive to said speed decrement command signal for inhibiting the application of said low and high frequency reference pulse signals to said frequency divider during said defined period.