Microprocessor-based programmable logic controller

A programmable logic controller comprising

• an input/output device for inputting data indicating the actual status of external devices and for outputting signals indicating the desired status of the external devices,
• a main memory device storing universal instructions and sequence instructions,
• an arithmetic operation control unit connected to said main memory device for repeatedly and sequentially fetching the universal instructions and the sequence instructions and executing the same,
• switch means connected to said arithmetic operation control unit for assuming a first state when a universal instruction is accessed by said arithmetic operation control unit and assuming a second state when a sequence instruction is accessed by said arithmetic operation control unit,
• a first read only memory device storing microprograms including microinstructions used for executing the universal instructions and connected to said arithmetic operation control unit through said switch means for receiving designated addresses from said arithmetic operation control unit when said switch means is in said first state, and producing microinstructions of the designated addresses for controlling said arithmetic control unit for execution of the universal instructions,
• a second read only memory device storing microprograms including microinstructions used for executing the sequence instructions, and connected to said arithmetic operation control unit through said switch means for receiving designated addresses from said arithmetic operation control unit when said switch means is in said second state, and
• a sequence control unit connected to said second read only memory device and used for executing the sequence instructions,
• said second read only memory device producing microinstructions of the designated addresses for controlling said arithmetic operation control unit and sequence control unit for execution of the sequence instructions, and
• said sequence control unit being controlled by said second read only memory drive to receive data indicating the status of the external devices obtained through said input/output device and to execute the sequence instructions to produce signals indicating the desired status of the external devices.