QPSK Suppressed carrier with rotating reference phase

A method of communicating single channel binary coded data bits synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising phase modulating a suppressed carrier constant amplitude envelope at the rate of the clock frequency so that the carrier for sequential data bits is sequentially phase incremented 90.degree. in the same direction

• [I+(sgnK)](90.degree.)
• in response to first, second, third . . . (K)th sequential bits of the binary data respectively having first or second binary values, wherein
• .vertline.K.vertline.=K,
• I=0, 1, 2, 3 (initial phase condition)
• and
• (sgnK)=.+-.1
• depending upon rotation direction, each of the sequential increments being for the period of one clock cycle, at a receiver responding to the suppressed carrier signal to establish a sequence of rotating reference phases at the carrier frequency, said reference phases stepping 90.degree. in the same direction as the suppressed carrier
• [P+(sgnK)](90.degree.)
• where P is any one of 0, 1, 2 or 3 depending on the initial phase condition of the receiver during the intervals while the first, second, third . . . (K)th bits are modulating the suppressed carrier, and phase comparing the rotating reference phase with the phase of the suppressed carrier to derive sequential first, second, third . . . Kth d.c. levels indicative of the binary bit values during the first, second, third . . . Kth binary bits.

Apparatus for transmitting binary coded data capable of tolerating long term polarity ambiguity without performance loss, such as coded voide or address signals, comprising a source of clock signals, means for synchronizing bits of the binary coded data to the clock source, a pair of 90.degree. phase displaced sinusoidal modulating waveforms having a frequency .omega..sub.m equal to one quarter the bit rate of the synchronized data and represented by sin .omega..sub.m t and cos .omega..sub.m t, a carrier source and first and second orthogonal modulated channels having a frequency .omega..sub.c, and means responsive to the clock source and the modulating waveforms for directing alternate data bits to the first and second modulated channels in interleaved fashion so the respective modulating waveforms are inverted or not inverted in response to the associated data bit binary value to produce in an alternating and overlapped manners.+-.[(cos .omega..sub.mt) (cos .omega..sub.ct), and.+-.(sin .omega..sub.mt) (sin .omega..sub.ct)] (cos .omega..sub.m t) (cos .omega..sub.c t), and .+-.(sin .omega..sub.m t) (sin .omega..sub.c t) from respective first and second channels, the response to an associated data bit being limited to and synchronized with half-cycle intervals of unchanging polarity for the functions [cos .omega..sub.mt and sin .omega..sub.mt ] cos .omega..sub.m t and sin .omega..sub.m t.

Apparatus for transmitting binary coded data, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising a clock source having a predetermined frequency, means for synchronizing the data to the clock source, means for phase modulating a suppressed carrier offset quadrature phase shift key signal having a constant amplitude envelope at the rate of the clock frequency so the associated carrier-component phase is sequentially phase incremented 90.degree. in the same direction

• [I+(sgnK)](90.degree.)
• in response to first, second, third . . . (K)th sequential bits of the binary data respectively having first or second binary values, wherein
• .vertline.K.vertline.=K,
• I=0, 1, 2, 3 (initial phase condition),
• and
• (sgnK)=.+-.1
• depending upon the rotation direction, each of the sequential increments being for the period of one clock cycle.

Apparatus for detecting data from a suppressed carrier phase shift key signal modulated so the associated carrier-component phase is sequentially incremented 90.degree. in the same direction

• [I+(sgnK)](90.degree.)
• in response to first, second, third . . . (K)th sequential bits of the binary data respectively having first or second binary values, wherein
• .vertline.K.vertline.=K,
• I=0, 1, 2, 3 (initial phase condition),
• and
• (sgnK)=.+-.1
• depending upon the rotation direction each of the sequential increments being for the period of one clock cycle, comprising means responsive to the suppressed carrier signal for establishing a sequence of rotating reference phases at the carrier frequency, said reference phases being incremented 90.degree. in the same direction as the suppressed carrier during the intervals while the first, second, third . . . (K)th bits are modulating the suppressed carrier, and means for phase comparing the rotating reference phase with the phase of the suppressed carrier signal to derive sequential first, second, third . . . (K)th d.c. levels indicative of the binary bit values during the first, second, third . . . (K)th binary bits.

Apparatus for communicating single-channel binary coded data bits, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising a clock source having a predetermined frequency, means for synchronizing the data to the clock source, means for phase modulating a suppressed carrier constant amplitude envelope at the rate of the clock frequency so that the carrier phase for sequential data bits is sequentially phase incremented 90.degree. in the same direction

• [I+(sgnK)](90.degree.)
• in response to first, second, third . . . (K)th sequential bits of the binary data respectively having first or second binary values, wherein
• .vertline.K.vertline.=K,
• I=0, 1, 2, 3 (initial phase condition)
• and
• (sgnK)=.+-.1
• depending upon rotation direction, each of the sequential increments being for the period of one clock cycle;
• at a receiver, means responsive to the suppressed carrier signal for establishing a sequence of rotating reference phases at the carrier frequency, said reference phases stepping 90.degree. in the same direction as the suppressed carrier
• [P+(sgnK)](90.degree.)
• where P is any one of 0, 1, 2 or 3 depending on the initial phase condition of the receiver during the intervals while the first, second, third. . . Kth bits are modulating the suppressed carrier, and means for phase comparing the rotating reference phase with the phase of the suppressed carrier to derive sequential first, second, third, . . . Kth d.c. levels indicative of the binary bit values during the first, second, third . . . Kth binary bits.

A method of communicating a singlechannel input serial data stream synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising separating the serial data stream into two time interleaved serial components each responding proportionally to alternate data sample values alternately in a direct polarity sense and in an inverted polarity sense, amplitude modulating quadrature phase carrier components with said interleaved components, summing said modulated quadrature phase carrier components to produce a suppressed carrier having an effective sequence of quadrature phase modulated carrier components incremented in a constant direction in 90.degree. phase steps in response to and in synchronism with data samples of the serial stream, whereby the carrier phase of each step is additionally phase shifted by 0.degree. or 180.degree. in response to the data samples, responding to the suppressed carrier to establish a phase for two quadrature phase coherent demodulation channels, alternately inverting and non-inverting the demodulated signals in each channel to provide an equivalent rotating phase demodulation reference stepping in synchronism with the phase of the suppressed carrier, and re-combining the time-interleaved components from the channels to provide a single-channel serial data stream substantially the same as the input data stream or its complement.

A method of communicating a single-channel input serial binary data stream synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising separating the serial data stream into two time interleaved serial components each responding to alternate binary data values alternately in a direct polarity sense and in an inverted polarity sense, bi-phase modulating quadrature phase carrier components with said interleaved components, summing said modulated quadrature phase carrier components to produce a suppressed carrier having an effective sequence of quadrature phase modulated carrier components incremented in a constant direction in 90.degree. phase steps in response to and in synchronism with data bits of the stream, whereby the carrier phase of each step is additionally phase shifted by 0.degree. or 180.degree. in response to the data samples, responding to the suppressed carrier to establish a phase for two quadrature phase coherent demodulation channels, alternately inverting and non-inverting the demodulated signals in each channel to provide an equivalent rotating phase demodulation reference stepping in synchronism with the phase of the suppressed carrier, and recombining the time-interleaved components from the channels to provide a single-channel serial data stream substantially the same as the input data stream or its complement.

A method of transmitting binary coded serial data bits synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising the steps of dividing the data stream into first and second separate time-interleaved components synchronized with the frequency and phase of the clock source, controlling the polarity of a first modulating wave synchronized with and at the frequency of the clock source in response to the value of the first component so that alternate half cycles of the first modulating wave having first and second polarities in response to the first component respectively having first and second values, the remaining half cycles of the first wave having first and second polarities in response to the first component respectively having second and first values, controlling the polarity of a second modulating wave synchronized with and at the frequency of the clock source in response to the value of the second component, alternate half cycles of the second modulating wave having first and second polarities in response to the second component respectively having first and second values, the remaining half cycles of the second modulating wave having first and second polarities in response to the second component respectively having second and first values, said first and second modulating waves being displaced 90.degree. relative to each other, modulating first and second mutually orthogonal components of a carrier with the first and second modulating waves to derive first and second modulated waves, and linearly combining the first and second modulated waves.

A method of transmitting binary coded serial data bits synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising the steps of dividing the data stream into first and second separate time-interleaved components having a symbol rate one-half that of the serial bits, controlling the polarity of a first modulating wave in response to the value of symbols in the first component so that a first set of values of adjacent symbols causes a reversal of the modulating wave polarity at a mid-point of the adjacent symbols and adjacent symbols having an opposite set of values cause the first modulating wave polarity to remain constant for the duration of the adjacent opposite valued symbols, controlling the polarity of a second modulating wave in response to the value of the symbols in the second component so that a first set of values of adjacent symbols causes a reversal of the second modulating wave polarity at a mid-point of the adjacent symbols and adjacent symbols having the opposite set of values cause the second modulating wave polarity to remain constant for the duration of the adjacent opposite valued symbols, each modulating wave having a zero point in time coincidence with a polarity change thereof, the first and second modulating waves being phase displaced 90.degree. relative to each other, modulating first and second mutually orthogonal components of a carrier with the first and second modulating waves to derive first and second modulated waves, and linearly combining the first and second modulated waves.

Apparatus for transmitting binary coded serial data bits synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising means for dividing the data stream into first and second separate time-interleaved components synchronized with the frequency and phase of the clock source, means for controlling the polarity of a first modulating wave synchronized with and at the frequency of the clock source in response to the value of the first component so that alternate half cycles of the first modulating wave having first and second polarities in response to the first component respectively having first and second values, the remaining half cycles of the first wave having first and second polarities in response to the first component respectively having second and first values, and for controlling the polarity of a second modulating wave synchronized with and at the frequency of the clock source in response to the value of the second component, alternate half cycles of the second modulating wave having first and second polarities in response to the second component respectively having first and second values, the remaining half cycles of the second modulating wave having first and second polarities in response to the second component respectively having second and first values, said first and second modulating waves being displaced 90.degree. relative to each other, means for modulating first and second mutually orthogonal components of a carrier with the first and second modulating waves to derive first and second modulated waves, and means for linearly combining the first and second modulated waves.

Apparatus for transmitting binary coded serial data bits synchronized to a clock source having a predetermined frequency, said data being capable of tolerating long term polarity ambiguity without performance loss, such as coded voice and address signals, comprising means for dividing the data stream into first and second separate time-interleaved components having a symbol rate one-half that of the serial bits, means for controlling the polarity of a first modulating wave in response to the value of symbols in the first component so that a first set of values of adjacent symbols causes a reversal of the modulating wave polarity at a mid-point of the adjacent symbols and adjacent symbols having an opposite set of values cause the first modulating wave polarity to remain constant for the duration of the adjacent opposite valued symbols, and for controlling the polarity of a second modulating wave in response to the value of the symbols in the second component so that a first set of values of adjacent symbols causes a reversal of the second modulating wave polarity at a mid-point of the adjacent symbols and adjacent symbols having the opposite set of values cause the second modulating wave polarity to remain constant for the duration of the adjacent opposite valued symbols, each modulating wave having a zero point in time coincidence with a polarity change thereof, the first and second modulating waves being phase displaced 90.degree. relative to each other, means for modulating first and second mutually orthogonal components of a carrier with the first and second modulating waves to derive first and second modulated waves, and means for linearly combining the first and second modulated waves.