US 4,267,580 AGranted

CCD Analog and digital correlators

AssigneeThe United States of America as represented by the Secretary of the Navy

InventorsJames W. Bond, James M. Alsup, Jeffrey M. Speiser, Harper J. Whitehouse, Isaac Lagnado

Life of this patent

Estimating the term…

Loading patent…

Abstract

A charge-coupled device (CCD) analog and digital correlator comprises identical modules, each of which is a simple analog CCD correlator with digital input and output. Circuits are included: (1) for injecting charges proportional to the voltage sequences s(n) and r(n), where s(n) refers to the input signal, and r(n) relates to a reference signal, against which the input signal is correlated; (2) for non-destructively sensing and tapping each sample s(n) and r(n); (3) for forming the summation s(n)+r(n); (4) and finally for squaring s(n), r(n), and [s(n)+r(n)] in simple, floating gate MOSFET amplifiers. The amplifiers operate in their saturation region, and have outputs proportional to s.sup.2 (n), r.sup.2 (n), and [s(n)+r(n)].sup.2, which are then fed into a differential amplifier to produce s(n)r(n).

Claims12

Dependent claims

A convolver comprising:

a first, multi-tap, delay line at one end of which, for example the left end, is applied a signal s(n), the signals at the outputs of the various taps, starting from the left end, being s(0), s(1), . . . , s(N-1);
a second N-tap delay line, at the right end of which is applied a signal r(n), the outputs of this delay line, from the right end of the delay line, being r(0), r(1), . . . , r(N-1);
a plurality of N means for multiplying having two inputs, one input from each of the two delay lines, being paired as follows:
the s(0)th tap of the first delay line and the r(N-1)th output of the second delay line being connected to the left most means for multiplying, the s(1)th output of the first delay line and the r(N-2)th output of the second delay line being connected to the second means for multiplying, etc.;
each means for multiplying comprising:
a means for generating the signal corresponding to the square of the signal [s(n)+r(m-n)];
a means for generating the signal s.sup.2 (n);
a means for generating the signal r.sup.2 (m-n);
and
a means for taking the difference between the first-named signal and the other two signals to result in a remainder signal [2s(n)r(n-m).]2s(m)r(m-n);
the convolver further comprising:
a means for adding the N outputs of the multipling means the output of the adding means being the summation from n=0 to N-1 of the quantity s(n)r(m-n);
wherein:
all of the signals involved, including s(n), r(n) and s(n) r(m-n), are modulo numbers;
and wherein
the first and second delay lines, the multiplying means and the means for adding are implemented as charge-coupled devices.

13 more elements

A convolver comprising:

a first, multi-tap, delay line at one end of which, for example the left end, is applied a signal s(n), the signals at the outputs of the various taps, starting from the left end, being s(0), s(1), . . . , s(N-1);
a second N-tap delay line, at the right end of which is applied a signal r(n), the outputs of this delay line, from the right end of the delay line, being r(0), r(1), . . . , r(N-1);
a plurality of N means for multiplying having two inputs, one input from each of the two delay lines, being paired as follows:
the s(0)th tap of the first delay line and the r(N-1)th output of the second delay line being connected to the left most means for multiplying, the s(1)th output of the first delay line and the r(N-2)th output of the second delay line being connected to the second means for multiplying, etc.;
each means for multiplying comprising:
means for generating the signal corresponding to the square of the signal [s(n)+r(m-n)];
a means for generating the signal s.sup.2 (n);
a means for generating the signal r.sup.2 (m-n);
and
a means for taking the difference between the first-named signal and the other two signals to result in a remainder signal 2s(m)r(m-n);
the convolver further comprising:
a means for adding the N outputs of the multiplying means, the output of the adding means being the summation from n=0 to N-1 of the quantity s(n)r(m-n);
wherein
all of the signals, including signals s(n), r(n) and s(n) r(m-n) correspond to radix numbers, excluding the radix 2 and 10;
and wherein
the first and second delay lines, the multiplying means and the means for adding are implemented as charge-coupled devices.

13 more elements

A correlator structure comprising:

an even number plurality of convolvers each convolver comprising:
a first, multi-tap, delay line at one end of which, for example the left end, is applied a signal s(n), the signals at the outputs of the various taps, starting from the left end, being s(0), s(1), . . . , s(N-1);
a second N-tap delay line, at the right end of which is applied a signal r(n), the outputs of this delay line, from the right end of the delay line, being r(0), r(1), . . . , r(N-1);
a plurality of N multipliers having two inputs, one input from each of the two delay lines, being paired as follows:
the s(0)th tap of the first delay line and the r(N-1)th output of the second delay line being connected to the left most multiplier, the s(1)th output of the first delay line and the r(N-2)th output of the second delay line being connected to the second multiplier, etc.;
wherein the means for multiplying comprises:
a means for generating the signal corresponding to the square of the signal [s(n)+r(m-n)];
a means for generating the signal s.sup.2 (n);
a means for generating the signal r.sup.2 (m-n);
and
a means for taking the difference between the first-named signal and the other two signals to result in a remainder signal 2s(n)r(n-m);
a means for adding the N outputs of the multipliers, the output of the adding means being the summation from n=0 to N-1 of the quantity s(n)r(m-n);
the signals s(n), r(n) and s(n) r(m-n) being all modulo numbers;
and wherein the means for adding comprises:
a plurality of N/2means for summing, each having two inputs which comprise outputs from two of the means for multiplying, each means for summing having an output;
a plurality of N/4 means for summing, having two inputs from two of the plurality of N/2 means for summing, each of the means for summing having an output, etc., the outputs of two summers being connected to other summers until there is only summer left having two inputs and one output;
the correlator structure further comprising:
a first means for rectifying, whose input signal is r(n) and whose output signals are r.sup.+ (n) and r.sup.- (n), the r.sup.+ (n) output being connected to the inputs of two first delay lines, the r.sup.- (n) output being connected to two other first delay lines;
a second means for rectifying, which converts an input signal s(n) into two output signals s.sup.+ (n) and s.sup.- (n), the s+(n) output signal being connected to two second delay lines, the s.sup.- (n) output signal being connected to two other second delay lines;
the signals r(n), r.sup.+ (n) and r.sup.- (n) and s(n), s.sup.+ (n) and s.sup.- (n) being defined by Equations (3), (4) and (5);
a first means for differencing, whose output signal comprises the difference of its two input signals, one input being connected to the output of an adding means of one of the convolvers, the other input being connected to the output of a means for adding of another convolver;
a second means for differencing, whose two inputs are connected to the outputs of two means for adding of two other convolvers;
and
an output means for summing whose two inputs comprise the outputs of the two differencing means and whose output is twice the summation;
the first and second delay lines, the multipliers and the means for adding being implemented as charge-coupled devices.

22 more elements

A correlator structure comprising:

an even number plurality of convolvers each convolver comprising:
a first, multi-tap, delay line at one end of which, for example the left end, is applied a signal s(n), the signals at the outputs of the various taps, starting from the left end, being s(0), s(1), . . . , s(N-1);
a second N-tap delay line, at the right end of which is applied a signal r(n), the outputs of this delay line, from the right end of the delay line, being r(0), r(1), . . . , r(N-1);
a plurality of N means for multiplying having two inputs, one input from each of the two delay lines, being paired as follows:
the s(0)th tap of the first delay line and the r(N-1)th output of the second delay line being connected to the left most multiplier, the s(1)th output of the first delay line and the r(N-2)th output of the second delay line being connected to the second multiplier, etc.;
the means for multiplying comprising:
a means for generating the signal corresponding to the square of the signal [s(n)+r(m-n)];
a means for generating the signal s.sup.2 (n);
a means for generating the signal r.sup.2 (m-n);
and
a means for taking the difference between the first named signal and the other two signals to result in a remainder signal 2s(n)r(n-m);
a means for adding the N outputs of the multiplying means, the output of the adding means being the summation from n=0 to N-1 of the quantity s(n)r(m-n);
all signals, including signals s(n), r(n) and s(n) r(m-n) corresponding to radix numbers, excluding the radix 2 and 10;
the means for adding comprising:
a plurality of N/2 means for summing, each having two inputs which comprise outputs from two of the means for multiplying, each means for summing having an output;
a plurality of N/4 means for summing, having two inputs from two of the plurality of N/2 means for summing, each of the means for summing having an output, etc., the outputs of two summers being connected to other summers until there is only summer left having two inputs and one output;
the correlator structure further comprising:
a first means for rectifying, whose input signal is r(n) and whose output signal are r.sup.+ (n) and r.sup.- (n), the r.sup.+ (n) output being connected to the inputs of two first delay lines, the r.sup.- (n) output being connected to two other first delay lines;
a second means for rectifying, which converts an input signal s(n) into two output signals s.sup.+ (n) and s.sup.- (n), the s+(n) output signal being connected to two second delay lines, the s.sup.- (n) output signal being connected to two other second delay lines;
the signals r(n), r.sup.+ (n) and r.sup.- (n) and s(n), s.sup.+ (n) and s.sup.- (n) being defined by Equations (3), (4) and (5);
a first means for differencing, whose output signal comprises the difference of its two input signals, one input being connected to the output of an adding means of one of the convolvers, the other input being connected to the output of a means for adding of another convolver;
a second means for differencing, whose two inputs are connected to the outputs of two means for adding of two other convolvers;
and
an output means for summing whose two inputs comprise the outputs of the two differencing means and whose output is twice the summation;
and wherein
the first and second delay lines, the multipliers and the means for adding are implemented as charge-coupled devices.

23 more elements

Dependencies are inferred from the claim text.