# US 4,264,382 A · Method for making a lateral PNP or NPN with a high gain utilizing reactive ion etching of buried high conductivity regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,264,382 A - Document ID: US4264382A - Status: Granted - Kind: A - Application number: 06/084,213 - Filed: 1979-10-12 - Granted: 1981-04-28 - Earliest claimed: 1978-05-25 - Assignees: International Business Machines Corporation - Inventors: Narasipur G. Anantha; Harsaran S. Bhatia; Santosh P. Caur; Hans B. Pogge - Web page: https://patentgrep.com/patent/US4264382A ## CPC - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 10/60: Lateral BJTs - H10D 84/0114: {the components including vertical BJTs and lateral BJTs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/63: Combinations of vertical and lateral BJTs - H10P 50/242: {of Group IV materials} - H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages. The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region. The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. ## Claims ### Claim 1 The method for making lateral PNP transistors comprising: providing a silicon semiconductor body having an N+ buried region therein; reactively ion etching regions of said body to form openings in the areas where dielectric isolation is desired to isolate regions of monocrystalline silicon; the etch rate of the said reactive ion etching is adjusted to cause a preferential etching of the said N+ region so that a portion of the said N+ region is removed and monocrystalline silicon remains above this removed portion; filling the said openings with a dielectric material wherein a portion of said monocrystalline region has a dielectric material under this region; simultaneously forming the P type emitter and collector regions with the emitter region being formed in said portion of said monocrystalline region having dielectric isolation thereunder wherein there is no vertical junction between the said P type emitter and said buried N+ region; and making electrical contacts to the emitter, base and collector regions to form said PNP lateral transistor. ### Claim 2 (depends on 1) The method of claim 1 wherein an N+ region is formed in the said semiconductor body for the base contact of said PNP transistor. ### Claim 3 (depends on 1) The method of claim 1 wherein the extension of said dielectric material under said monocrystalline region between about 1 to 3 microns. ### Claim 4 (depends on 1) The method of claim 1 wherein the reactive ion etching is accomplished in a chlorine-argon ambient. ### Claim 5 (depends on 4) The method of claim 4 wherein the said chlorine specie ambient has a pressure of between 0.20 to 1.5 microns of mercury, said chlorine specie in said ambient being between about 2 and 15 percent, and the etch rate between about 0.07 and 0.20 microns per minute. ### Claim 6 (depends on 1) The method of claim 1 wherein the said dielectric material is silicon dioxide. ### Claim 7 (depends on 1) The method of claim 1 wherein the said dielectric material is deposited in said openings by SiH.sub.4 /N.sub.2 O/N.sub.2. ### Claim 8 (depends on 1) The method of claim 1 wherein the dimensions of said emitter region are 1 by 1 to 3 by 3 microns squared. ### Claim 9 (depends on 1) The method of claim 1 wherein a vertical NPN transistor is formed simultaneously with said lateral PNP transistor. ### Claim 10 (depends on 2) The method of claim 2 wherein vertical NPN and a lateral PNP transistors are formed simultaneously in a process that includes forming the emitter of said NPN at the same time as the base contact of said PNP. ### Claim 11 The method for making lateral NPN transistors comprising: providing a silicon semiconductor body having a P+ buried region therein; reactively ion etching regions of said body to form openings in the areas where dielectric isolation is desired to isolate regions of monocrystalline silicon; the etch rate of the said reactive ion etching is adjusted to cause a preferential etching of the said P+ region so that a portion of the said P+ region is removed and monocrystalline silicon remains above this removed portion; filling the said openings with a dielectric material wherein a portion of said monocrystalline region has a dielectric material under this region; simultaneously forming the N type emitter and collector regions with the emitter region being formed in said portion of said monocrystalline region having dielectric isolation thereunder wherein there is no vertical junction between the said N type emitter and said buried P+ region; and making electrical contacts to the emitter, base and collector regions to form said NPN lateral transistor.