# US 4,263,647 A · Fault monitor for numerical control system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,263,647 A - Document ID: US4263647A - Status: Granted - Kind: A - Application number: 06/009,938 - Filed: 1979-02-07 - Granted: 1981-04-21 - Earliest claimed: 1979-02-07 - Assignees: Allen-Bradley Company, Inc. - Inventors: Gregory L. Merrell; Theodore L. Bernhard - Web page: https://patentgrep.com/patent/US4263647A ## CPC - G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs} - G05B 19/4063: Monitoring general control system (G05B19/4062 takes precedence) - G06F 11/0724: {in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80)} - G06F 13/32: using combination of interrupt and burst mode transfer - G05B 2219/34466: Bad circuits, watchdog, alarm, indication - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract Associated with each processor in a multiprocessor numerical control system is a watchdog timer circuit which is periodically reset by its processor under normal operating conditions. If a malfunction should occur in one of the processors, its watchdog timer is not reset and it times out. A fault monitor line connects to each watchdog timer circuit and an emergency stop circuit, and when a malfunction occurs in any one of the processors, this condition is indicated to all the processors and to the emergency stop circuit. ## Claims ### Claim 1 In a numerical control system having a plurality of separately operating programmed processors which operate together to control a machine tool, the improvement therein comprising: a set of watchdog timer circuits, one associated with each of said processors and each watchdog timer circuit having an input terminal which periodically receives a signal from its associated processor that resets the watchdog timer and each having an output terminal at which a fault indicating logic signal is generated when the watchdog timer is not reset by its associated processor within a preset time interval; a fault monitor line coupled to the output terminal of each of said watchdog timer circuits; and an emergency stop circuit coupled to said fault monitor line and being operable to indicate a malfunction condition when any one of said watchdog timer circuits generates a fault indicating logic signal. ### Claim 2 (depends on 1) The improved numerical control system as recited in claim 1 in which said fault monitor line is coupled to each of said processors through means for interrupting the normal operation of said processors when a fault indicating logic signal is generated on the fault monitor line. ### Claim 3 (depends on 2) The improved numerical control system as recited in claim 2 in which each programmed processor includes a memory which stores a watchdog timer interrupt service routine when it is interrupted by the fault indicating logic signal on said fault monitor line. ### Claim 4 (depends on 1, 2, 3) The improved numerical control system as recited in claim 1, 2 or 3 in which said emergency stop circuit includes a relay having a coil which is energized when the fault indicating logic signal is not present on said fault monitor line and which is deenergized when the fault indicating logic signal is present. ### Claim 5 In a numerical control system having a plurality of separately operating programmed processors which operate together to control a machine tool, the improvement therein comprising: a set of fault detecting circuits, one associated with each of said processors and each fault detecting circuit being operable to generate a fault indicating logic signal at its output when a malfunction in its associated processor is detected; means connecting the output of each fault detecting circuit to an interrupt request terminal on its associated processor; and a fault monitor line coupled to the output terminal of each fault detecting circuit to apply a fault indicating logic signal generated by any one of said fault detecting circuits to the output terminals of all said fault detecting circuits, wherein the generation of a fault indicating logic signal by any one of said fault detecting circuits causes an interrupt request signal to be applied to the interrupt request terminal on each processor in the numerical control system. ### Claim 6 (depends on 5) The improved numerical control system as recited in claim 5 in which each processor is responsive to an interrupt request signal applied to its interrupt request terminal to terminate performance of its current function and perform a preselected function. ### Claim 7 (depends on 5, 6) The improved numerical control system as recited in claim 5 or 6 in which an emergency stop circuit is coupled to said fault monitor line and is operable to indicate a malfunction condition when any one of said fault detecting circuits generates a fault indicating logic signal.