US 4,253,146 AGranted

Module for coupling computer-processors

AssigneeBurroughs Corporation

InventorsClifford J. Bellamy, John O. Besemer

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Abstract

A Global Memory Module (GMM) and a system hierarchy of processors is described which provides access to a plurality of addressable memory storage units. A multiple number of processors or computer systems are connected to one or more Global Memory Modules whereby memory resources may be shared by multiple processor systems and where control and communications are provided between the processors through the Global Memory Modules. The Global Memory Module may be organized into a hierarchy of Global Memory Module systems whereby processors attached to "lower level" GMM systems may access memory in "higher level" GMM systems. Means are provided whereby a processor in one GMM system may send commands and messages to a processor in another GMM system. Means are provided by which one processor can address another specific processor in the system network or whereby one processor can address an "available" processor in a system designated under a system name, and the network will choose the processor which is "idle" or, if there is no idle processor available, will then choose a processor which is "not engaged", that is to say, a processor which when it finishes its currently scheduled activities, will then be available for processing of a received command and message. The Global Memory Module has input ports for connection to a local individual processor or to another Global Memory Module. The GMM has (1) a Global Memory Control Section for handling requests for access to memory and (2) a Global System Control Section for control of messages between a processor and its GMM.

Claims14

Dependent claims

A module for coupling a plurality of local processors having local memory with a plurality of shareable memory storage units and controllers, said module being designated as a global memory module, said module comprising:

(a) a plurality of discrete memory storage units, each of said units being identified by a number (i) via manually settable identification means in a system controller, and each of said memory storage units includes:
(a1) a series of addressable memory locations having addresses which increase sequentially in number value;
(a2) and wherein the addresses in each higher numbered memory storage unit (i+1) has addresses greater in value than any of the addresses in any lower numbered memory storage unit (i);
(b) a memory controller connected to said memory storage units and to said plurality of local processors, said memory controller including:
(b1) means to read from, or write into, an addressed location in said memory storage units;
(b2) means to transfer a memory request from a processor to a repeater bus should the requested memory address exceed the highest address available in said plurality of memory storage units;
(b3) a repeater bus to convey memory address requests placed thereon to a global module external to said global memory module;
(c) a plurality of input ports, each of said ports permitting bus connection to a separate local processor and wherein each of said input ports includes:
(c1) a requester port adapter for storing and communicating memory requests made, on said discrete memory storage units, from said local processor to said memory controller;
(c2) a processor port adapter for storing and communicating control, informational and synchronization signals from said local processor to a system controller, said processor port adapter including:
(c2-1) access control register means which map each of said numbered memory storage units with bit signals that permit or deny access to selected memory areas by the connected local processor;
(d) a system controller connected via said input ports to each of said separate local processors, said system controller including:
(d1) means to transfer data or commands stored in a processor port adapter to its associated local processor;
(d2) bus means to convey commands and data to a global memory module external to said global memory module.

11 more elements

A network of replicatable communication-control modules wherein each communication-control module connects a plurality of local processors, each having a local memory resource, to a plurality of shareable memories in the said communication-control module, and wherein a plurality of said replicatable communication-control modules are connected in a hierarchical series of levels such that the topmost module and its shareable memories and its locally connected processors are designated as level "0", and the subordinate levels are designated as levels "1", "2", "3", etc., the network comprising:

(a) a plurality of communication-control modules, each of said communication-control modules comprising:
(a1) a plurality of discrete memory storage units, each of said units being identified by a number (i) via settable identification means in a system controller, and each of said memory storage units including:
(a1-1) a series of addressable memory locations having addresses which increase sequentially in number value;
(a1-2) and wherein the addresses in each higher numbered memory storage unit (i+1) has addresses greater in value than any of the addresses in any lower-numbered memory storage unit (i);
(a2) a memory controller connected to said memory storage units and to a plurality of said local processors, said memory controller including:
(a2-1) means to read from or write into an address location in said memory storage units;
(a2-2) means to transfer a memory request from a processor to a repeater port should the requested memory address exceed the highest address available in said plurality of memory storage units;
(a2-3) a repeater port having means to convey memory addresses on a repeater bus;
(a2-4) a repeater bus connected to said repeater port to convey memory address requests placed thereon to the input port of a higher level communication-control module;
(a3) a plurality of input ports, each of said input ports providing for bus connection to a separate local processor and/or connection from a repeater bus of a lower level repeater port and wherein each of said input ports includes:
(a3-1) a requester port adapter for storing and communicating memory requests made on said discrete memory storage units from a requesting local processor to said memory controller;
(a3-2) a processor port adapter for storing and communicating control, informational and synchronization signals from said local processor to a system controller, said processor port adapter including:
(a3-2a) access control register means which map each of said numbered memory storage units with bit signals that permit or deny access to selected memory areas by the associated local processor;
(a4) a system controller connected via said input ports to each of said local processors, said system controller including:
(a4-1) means to transfer data or commands stored in a processor port adapter to its associated local processor;
(a4-2) system controller-adapter means connected to an external bus to convey commands and data to or from a higher level communication-control module;
(b) a repeater bus connected to said repeater port for transmitting memory address and memory data between a lower level and a higher level communication-control module;
(c) a system control bus connected to said system controller adapter for connecting a lower level system controller with the next higher level system controller;
(d) a plurality of processors wherein each communication-control module at a given level connects a group of processors to its input ports at that given level.

16 more elements

Dependencies are inferred from the claim text.