Redundant memory circuit
AssigneeIntel Corporation
InventorsFrederick Tsang, Gregory A. Kannal, Marcian E. Hoff, Jr.
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Abstract
A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.
Claims12
A redundant memory circuit for a memory array comprising:
- a memory having a preselected number of rows and columns having addresses associated therewith, each of said rows and columns having an individual decoder coupled thereto, and one or more redundant rows or columns having initially unspecified addresses associated therewith, each of said redundant rows or columns having an individual redundant decoder coupled thereto;
- programming means for causing the redundant decoders coupled to said redundant rows or columns having initially unspecified addresses to respond only to the addresses of defective rows or columns having addresses associated therewith;
- and
- means for disabling said defective rows or columns having addresses associated therewith.
Dependencies are inferred from the claim text.