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US 4,247,905 AGranted
Memory clear system
AssigneeSharp Kabushiki Kaisha
InventorsYukihiro Yoshida, Toru Izaki, Toshiyuki Maegawa, Satoshi Tominaga
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Abstract
A memory clear method useful to clear a plurality of words contained in a memory from a specific address to an address at the same time. An address register is provided for this purpose. In one preferred form, the address register is responsive to a CX key indicating a memory clear operation, a , key indicating start of the memory clear operation and 0 to 9 digit keys identifying a memory address for the memory clear operation.
Claims8
A system for automatically and selectively clearing all or a portion of a memory means having a capacity to store a plurality of words comprising:
- first means for instructing said system to begin a memory clear operation;
- second means for designating a starting address within said plurality of the words for the purpose of said memory clear operation;
- means responsive to said second means for setting a memory address register at said designated starting address;
- third means for entering a value n into said system representing the number of said plurality of words in said memory means undergoing clearing;
- fourth means for instructing start of the clear operation;
- and
- control means for automatically and sequentially advancing the starting address in the address register a number of times equal to said value n entered into said system via said third means in response to instructing the clear operation via said fourth means, thereby automatically and selectively clearing a predetermined number n of said plurality of words in said memory means extending from said designated address to an end address in response to said first, second and fourth means, said control means including circuit means responsive to the presence and absence of actuation of said second means prior in sequence to said fourth means to automatically and selectively clear a portion or all, respectively, of said memory means.
4 more elements
A circuit means for selectively and automatically clearing all or a portion of a plurality of words from a memory in response to an initial series of input instructions comprising:
- a first memory means;
- first signal generating means for generating a first control signal indicating that a memory clear operation for said first memory means is desired;
- second signal generating means for generating a second control signal designating a starting address in said first memory representing the address of the first word in said plurality of words to be cleared;
- third signal generating means for generating a third control signal indicating that said memory clear operation should begin;
- a memory address register for said first memory means;
- logic control means responsive to said first, second and third control signals for setting said memory address register to a specific value equal to said starting address;
- said memory address register generating a first address output signal designating a specific location in said first memory means corresponding to said starting address;
- temporary storage means for storing a specific number in a temporary storage location, said specific number being equal to the number of words in said first memory means which constitute said plurality of words being cleared by said memory clear operation;
- and
- clock means for generating a clock signal including a plurality of periodically spaced pulses;
- said temporary storage means generating a said specific number of output signals in response to excitation by corresponding pulses of said clock signal;
- said logic control means incrementing said memory address register by a set value in response to each said plurality of output signals from said temporary storage means thereby causing said memory address register to generate a sequence of incremental memory address signals indicative of the additional addresses in said first memory means corresponding to said plurality of words undergoing said memory clear operation;
- a said sequence of incremental memory address signals being generated each time said memory address register is incremented by a said plurality of output signals from said temporary storage menas, said first memory means being cleared at a series of additional locations in accordance with the address locations indicated by each said series of incremental memory address signals, said logic control means including sub-circuit means responsive to the presence and absence of actuation of said second signal generating means and prior in sequence to said third signal generating means to selectively clear a portion and all, respectively, of said first memory means.
10 more elements
Dependencies are inferred from the claim text.