Processing system with dual buses
AssigneeRockwell International Corporation
InventorDavid L. Richter
Life of this patent
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Abstract
A processing system is disclosed in which transfers between processors and memory are made on dual redundant buses. In a transfer, the transmitting unit sends the same information simultaneously on each of the buses. The receiving unit makes parity checks on each bus, and compares the information received on one bus with that received on the other bus. The receiving unit includes means for implementing a decision rule, based on these checks and comparison, to choose from which bus to take information, if either.
Claims13
In a data processing system of the kind wherein multiple devices such as processors and memory modules communicate amongst themselves by transmitting in parallel a plurality of bits on a bus from a sending device to an addressed device, with each of said devices typically being capable of acting as a sending or an addressed device, the improvement comprising:
- a first bus having a first plurality of electrical signal conductors with the capacity for carrying in parallel a plurality of bits including a device address and a set of bits which can include data;
- a second bus having a second plurality of electrical signal conductors, of at least the same capacity as said first bus;
- an interface at each device capable of acting as a sending and addressed device, including
- means for simultaneously transmitting in parallel a plurality of bits on conductors of said first bus, and for transmitting the same bits on conductors of the second bus;
- means for examining transmitted bits as received on each bus for an error involving any number of bits, including means for comparing every bit in said set of bits on said first bus with the corresponding bit in said set of bits on the second bus, and for generating an indication of a good comparison only when all the compared bits match;
- and
- means, responsive to the results of said examining, for computing whether to utilize said set of bits received on the first bus and whether to utilize said set of bits received on the second bus.
A data processing system, comprising:
- p1 a first bus including a plurality of electrical signal conductors;
- a second bus including a second plurality of electrical signal conductors;
- at least one processor and at least one memory unit, each such processor and memory unit including transmitting means and receiving means in order for a processor to send signals on said buses to a memory unit and for a memory unit to send signals on said buses to a processor,
- said transmitting means including means for transmitting a plurality of digital signals on conductors of said first bus, and for transmitting said same digital signals on the conductors of the second bus, said digital signals including a set of signals which can include data,
- a parity check bit applicable to said set of signals, an address capable of designating a selected receiving means, and a parity check bit applicable to said address,
- said receiving means including means for receiving signals from both said buses including means for computing from the received signals whether to utilize said set of signals received on said first bus and whether to utilize said set of signals received on said second bus, said means for computing including,
- means for detecting errors involving any number of bits by comparing said set of signals received on said first bus with said set of signals received on said second bus, and generating an indication of a good comparison only when all the compared bits match,
- means for checking signals received on each of said buses, including said set of signals, with respect to the parity check bit applicable to said set,
- means for comparing said address as received on said buses with an address designating said means for receiving signals, and
- means for checking signals received on each of said buses with respect to the parity check bit applicable to said address,
- whereby said buses provide multiple paths for the transmission of signals back and forth between a processor and a memory unit.
Dependencies are inferred from the claim text.