Power line disturbance detector circuit

Abstract

A power line disturbance (PLD) detector circuit includes a digital counter which is driven by pulses provided by a clock in an associated data processing system. The PLD detector circuit includes a comparator amplifier for comparing primary AC power to a DC reference voltage on a cycle-by-cycle basis. The amplifier generates a reset pulse once during each AC cycle as long as the AC voltage exceeds the DC reference voltage. When a decoder circuit detects a count outside the range of counts attained by the digital counter between normally occurring reset pulses, the decoder circuit responds by generating a PLD signal. The PLD signal is provided both to the associated data processing system and to a Power On Reset circuit. The Power On Reset circuit is initialized by the PLD signal, permitting the circuit to respond consistently upon subsequent restoration of power.

Dependencies are inferred from the claim text.