US 4,242,755 AGranted

Circuit arrangement for decoding digital signals

AssigneeThomson-CSF

InventorPierre Gauzan

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Abstract

A demodulator for binary messages of the diphase type comprises a sampling circuit controlled by a local clock whose cycle is approximately 1/n.sup.th of the bit length of the incoming signals (with n=8 in a specific instance), this circuit deriving (n-2) samples from each message bit which are then analyzed in a programmed memory to determine whether the bit being sampled has one of six acceptable configurations, namely a bit of logical value "0" or "1" in either a normal, a leading or a lagging position with reference to a decoding interval T equaling n clock cycles. If a different configuration is detected, an error signal is generated. The decoding interval is measured by a counter, stepped by the local clock, which is adjusted by recalibrating commands from the programmed memory to shorten or lengthen the next decoding interval when a bit is found to lead or lag by a full clock cycle, thereby restoring the normal relative time position of the message bits and the decoding interval. A validation signal emitted by the bit analyzer in the presence of an acceptable configuration enables the generation of a synchronization pulse at a predetermined time in the decoding interval to mark the instant at which the received message bit can be correctly read either in a reconstituted bit sequence or in the original binary pulse train delayed by one interval T of n clock cycles.

Claims12

Dependent claims

A demodulator for binary message signals with bits distinguished by a characteristic phasing of two voltage levels, comprising:

local timing means for establishing a train of clock pulses with a cycle T1;
signal-generating means controlled by said clock pulses to establish a decoding interval T normally equaling n clock cycles T1 where n is an integer equal to at least 3;
sampling means connected to receive incoming message signals with bits whose length T' approximately equals said decoding interval T and to derive a plurality of samples from each of said bits;
bit-analyzing means connected to said sampling means for receiving therefrom at least some of the samples of an incoming message bit during each decoding interval in response to a transfer command from said signal-generating means, said bit-analyzing means being programmed to distinguish between predetermined acceptable configurations of bit samples and nonacceptable configurations differing therefrom and to discriminate among centered and off-centered acceptable configurations, with emission of a validating signal in the presence of any acceptable configuration and of a recalibration command in the presence of an off-centered configuration, said signal-generating means being responsive to said recalibrating command for altering the next decoding interval by one clock cycle T1 to re-establish a normal time position between said decoding interval and the following message bits;
and
circuit means connected to said bit-analyzing means for receiving said validating signal therefrom and controlled by said signal-generating means for emitting a synchronizing pulse, in the presence of said validating signal, at a predetermined time in each decoding interval.

3 more elements

Dependencies are inferred from the claim text.